linux-kernel - Re: [PATCH v2] Support rv32 ULEB128 test

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Message-ID: <7b27e5db-16b8-400e-a94b-a36f65205654@infradead.org>
Date:   Wed, 6 Dec 2023 09:00:38 -0800
From:   Randy Dunlap <rdunlap@...radead.org>
To:     Charlie Jenkins <charlie@...osinc.com>,
        Paul Walmsley <paul.walmsley@...ive.com>,
        Palmer Dabbelt <palmer@...belt.com>,
        Albert Ou <aou@...s.berkeley.edu>, Ron Economos <re@...z.net>
Cc:     Palmer Dabbelt <palmer@...osinc.com>,
        linux-riscv@...ts.infradead.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH v2] Support rv32 ULEB128 test

Hi,

On 11/22/23 15:35, Charlie Jenkins wrote:
> Use opcodes available to both rv32 and rv64 in uleb128 module linking
> test.
> 
> Fixes: af71bc194916 ("riscv: Add tests for riscv module loading")
> Signed-off-by: Charlie Jenkins <charlie@...osinc.com>
> Reported-by: Randy Dunlap <rdunlap@...radead.org>
> Closes: https://lore.kernel.org/lkml/1d7c71ee-5742-4df4-b8ef-a2aea0a624eb@infradead.org/
> Tested-by: Randy Dunlap <rdunlap@...radead.org> # build-tested
> ---
> Support module linking tests on rv32 toolchains with uleb128 support.

I'm still seeing build errors on this test module.

Can someone get this patch merged, please?

Thanks.

> ---
> Changes in v2:
> - Drop patch covered in different series
> - Link to v1: https://lore.kernel.org/r/20231117-module_fixup-v1-0-62bb777f6825@rivosinc.com
> ---
>  arch/riscv/kernel/tests/module_test/test_uleb128.S | 8 ++++----
>  1 file changed, 4 insertions(+), 4 deletions(-)
> 
> diff --git a/arch/riscv/kernel/tests/module_test/test_uleb128.S b/arch/riscv/kernel/tests/module_test/test_uleb128.S
> index 90f22049d553..8515ed7cd8c1 100644
> --- a/arch/riscv/kernel/tests/module_test/test_uleb128.S
> +++ b/arch/riscv/kernel/tests/module_test/test_uleb128.S
> @@ -6,13 +6,13 @@
>  .text
>  .global test_uleb_basic
>  test_uleb_basic:
> -	ld	a0, second
> +	lw	a0, second
>  	addi	a0, a0, -127
>  	ret
>  
>  .global test_uleb_large
>  test_uleb_large:
> -	ld	a0, fourth
> +	lw	a0, fourth
>  	addi	a0, a0, -0x07e8
>  	ret
>  
> @@ -22,10 +22,10 @@ first:
>  second:
>  	.reloc second, R_RISCV_SET_ULEB128, second
>  	.reloc second, R_RISCV_SUB_ULEB128, first
> -	.dword 0
> +	.word 0
>  third:
>  	.space 1000
>  fourth:
>  	.reloc fourth, R_RISCV_SET_ULEB128, fourth
>  	.reloc fourth, R_RISCV_SUB_ULEB128, third
> -	.dword 0
> +	.word 0
> 
> ---
> base-commit: 9bacdd8996c77c42ca004440be610692275ff9d0
> change-id: 20231117-module_fixup-699787d9c567

-- 
~Randy