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Message-ID: <20231206185657.GC2692119@nvidia.com>
Date: Wed, 6 Dec 2023 14:56:57 -0400
From: Jason Gunthorpe <jgg@...dia.com>
To: Yi Liu <yi.l.liu@...el.com>
Cc: joro@...tes.org, alex.williamson@...hat.com, kevin.tian@...el.com,
robin.murphy@....com, baolu.lu@...ux.intel.com, cohuck@...hat.com,
eric.auger@...hat.com, nicolinc@...dia.com, kvm@...r.kernel.org,
mjrosato@...ux.ibm.com, chao.p.peng@...ux.intel.com,
yi.y.sun@...ux.intel.com, peterx@...hat.com, jasowang@...hat.com,
shameerali.kolothum.thodi@...wei.com, lulu@...hat.com,
suravee.suthikulpanit@....com, iommu@...ts.linux.dev,
linux-kernel@...r.kernel.org, linux-kselftest@...r.kernel.org,
zhenzhong.duan@...el.com, joao.m.martins@...cle.com,
xin.zeng@...el.com, yan.y.zhao@...el.com
Subject: Re: [PATCH v7 3/3] iommu/vt-d: Add iotlb flush for nested domain
On Fri, Nov 17, 2023 at 05:18:16AM -0800, Yi Liu wrote:
> +static int intel_nested_cache_invalidate_user(struct iommu_domain *domain,
> + struct iommu_user_data_array *array,
> + u32 *cerror_idx)
> +{
> + struct dmar_domain *dmar_domain = to_dmar_domain(domain);
> + struct iommu_hwpt_vtd_s1_invalidate inv_info;
> + u32 index;
> + int ret;
> +
> + /* REVISIT:
> + * VT-d has defined ITE, ICE, IQE for invalidation failure per hardware,
> + * but no error code yet, so just set the error code to be 0.
> + */
> + *cerror_idx = 0;
> +
> + for (index = 0; index < array->entry_num; index++) {
> + ret = iommu_copy_struct_from_user_array(&inv_info, array,
> + IOMMU_HWPT_DATA_VTD_S1,
> + index, __reserved);
> + if (ret) {
> + pr_err_ratelimited("Failed to fetch invalidation request\n");
> + break;
No error prints on ioctls!
> + if (inv_info.addr == 0 && inv_info.npages == -1)
> + intel_flush_iotlb_all(domain);
-1 is clearer written as U64_MAX - same remark for the comment
documenting it.
Jason
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