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Message-ID: <IA1PR20MB49531F7CAC79B0CEBB141222BB84A@IA1PR20MB4953.namprd20.prod.outlook.com> Date: Wed, 6 Dec 2023 08:41:00 +0800 From: Inochi Amaoto <inochiama@...look.com> To: Chao Wei <chao.wei@...hgo.com>, Chen Wang <unicorn_wang@...look.com>, Conor Dooley <conor@...nel.org>, Rob Herring <robh+dt@...nel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>, Paul Walmsley <paul.walmsley@...ive.com>, Palmer Dabbelt <palmer@...belt.com>, Albert Ou <aou@...s.berkeley.edu> Cc: Inochi Amaoto <inochiama@...look.com>, Jisheng Zhang <jszhang@...nel.org>, qiujingbao.dlmu@...il.com, dlan@...too.org, linux-riscv@...ts.infradead.org, devicetree@...r.kernel.org, linux-kernel@...r.kernel.org Subject: Re: [PATCH v2 4/4] riscv: dts: sophgo: add uart clock for Sophgo CV1800 series SoC > >Inochi Amaoto wrote: >> Add missing clocks of uart node for CV1800B and CV1812H. >> >> Signed-off-by: Inochi Amaoto <inochiama@...look.com> >> --- >> arch/riscv/boot/dts/sophgo/cv18xx.dtsi | 21 ++++++++++++++++----- >> 1 file changed, 16 insertions(+), 5 deletions(-) >> >> diff --git a/arch/riscv/boot/dts/sophgo/cv18xx.dtsi b/arch/riscv/boot/dts/sophgo/cv18xx.dtsi >> index c5642dd7cbbd..3f290a515011 100644 >> --- a/arch/riscv/boot/dts/sophgo/cv18xx.dtsi >> +++ b/arch/riscv/boot/dts/sophgo/cv18xx.dtsi >> @@ -5,6 +5,7 @@ >> */ >> >> #include <dt-bindings/interrupt-controller/irq.h> >> +#include <dt-bindings/clock/sophgo,cv1800.h> >> >> / { >> #address-cells = <1>; >> @@ -136,7 +137,9 @@ uart0: serial@...0000 { >> compatible = "snps,dw-apb-uart"; >> reg = <0x04140000 0x100>; >> interrupts = <44 IRQ_TYPE_LEVEL_HIGH>; >> - clocks = <&osc>; >> + clock-frequency = <25000000>; >> + clocks = <&clk CLK_UART0>, <&clk CLK_APB_UART0>; >> + clock-names = "baudclk", "apb_pclk"; >> reg-shift = <2>; >> reg-io-width = <4>; >> status = "disabled"; > >Hi Inochi, > >When there is a proper "baudclk" defined the driver should get the rate >(frequency) from that and the manually defined clock-frequency should not be >needed. > >/Emil > OK, thanks, I will remove this.
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