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Message-ID: <20231206083753.18186-2-jianjun.wang@mediatek.com>
Date: Wed, 6 Dec 2023 16:37:52 +0800
From: Jianjun Wang <jianjun.wang@...iatek.com>
To: Lorenzo Pieralisi <lpieralisi@...nel.org>,
Krzysztof WilczyĆski <kw@...ux.com>,
Rob Herring <robh@...nel.org>,
Bjorn Helgaas <bhelgaas@...gle.com>,
Matthias Brugger <matthias.bgg@...il.com>,
AngeloGioacchino Del Regno
<angelogioacchino.delregno@...labora.com>
CC: Ryder Lee <ryder.lee@...iatek.com>,
Jianjun Wang <jianjun.wang@...iatek.com>,
<linux-pci@...r.kernel.org>, <linux-mediatek@...ts.infradead.org>,
<linux-kernel@...r.kernel.org>,
<linux-arm-kernel@...ts.infradead.org>, <jieyy.yang@...iatek.com>,
<chuanjia.liu@...iatek.com>, <qizhong.cheng@...iatek.com>,
<jian.yang@...iatek.com>, <jianguo.zhang@...iatek.com>
Subject: [PATCH 1/2] PCI: mediatek: Allocate MSI address with dmam_alloc_coherent
Use 'dmam_alloc_coherent' to allocate the MSI address, instead of using
'virt_to_phys'.
Signed-off-by: Jianjun Wang <jianjun.wang@...iatek.com>
---
drivers/pci/controller/pcie-mediatek.c | 29 ++++++++++++++++++--------
1 file changed, 20 insertions(+), 9 deletions(-)
diff --git a/drivers/pci/controller/pcie-mediatek.c b/drivers/pci/controller/pcie-mediatek.c
index 66a8f73296fc..b080f7ca6da0 100644
--- a/drivers/pci/controller/pcie-mediatek.c
+++ b/drivers/pci/controller/pcie-mediatek.c
@@ -178,6 +178,7 @@ struct mtk_pcie_soc {
* @phy: pointer to PHY control block
* @slot: port slot
* @irq: GIC irq
+ * @msg_addr: MSI message address
* @irq_domain: legacy INTx IRQ domain
* @inner_domain: inner IRQ domain
* @msi_domain: MSI IRQ domain
@@ -198,6 +199,7 @@ struct mtk_pcie_port {
struct phy *phy;
u32 slot;
int irq;
+ dma_addr_t msg_addr;
struct irq_domain *irq_domain;
struct irq_domain *inner_domain;
struct irq_domain *msi_domain;
@@ -394,12 +396,10 @@ static struct pci_ops mtk_pcie_ops_v2 = {
static void mtk_compose_msi_msg(struct irq_data *data, struct msi_msg *msg)
{
struct mtk_pcie_port *port = irq_data_get_irq_chip_data(data);
- phys_addr_t addr;
/* MT2712/MT7622 only support 32-bit MSI addresses */
- addr = virt_to_phys(port->base + PCIE_MSI_VECTOR);
msg->address_hi = 0;
- msg->address_lo = lower_32_bits(addr);
+ msg->address_lo = lower_32_bits(port->msg_addr);
msg->data = data->hwirq;
@@ -515,18 +515,26 @@ static int mtk_pcie_allocate_msi_domains(struct mtk_pcie_port *port)
return 0;
}
-static void mtk_pcie_enable_msi(struct mtk_pcie_port *port)
+static int mtk_pcie_enable_msi(struct mtk_pcie_port *port)
{
u32 val;
- phys_addr_t msg_addr;
+ void *msi_vaddr;
- msg_addr = virt_to_phys(port->base + PCIE_MSI_VECTOR);
- val = lower_32_bits(msg_addr);
+ msi_vaddr = dmam_alloc_coherent(port->pcie->dev, sizeof(dma_addr_t), &port->msg_addr,
+ GFP_KERNEL);
+ if (!msi_vaddr) {
+ dev_err(port->pcie->dev, "failed to alloc and map MSI data\n");
+ return -ENOMEM;
+ }
+
+ val = lower_32_bits(port->msg_addr);
writel(val, port->base + PCIE_IMSI_ADDR);
val = readl(port->base + PCIE_INT_MASK);
val &= ~MSI_MASK;
writel(val, port->base + PCIE_INT_MASK);
+
+ return 0;
}
static void mtk_pcie_irq_teardown(struct mtk_pcie *pcie)
@@ -732,8 +740,11 @@ static int mtk_pcie_startup_port_v2(struct mtk_pcie_port *port)
val &= ~INTX_MASK;
writel(val, port->base + PCIE_INT_MASK);
- if (IS_ENABLED(CONFIG_PCI_MSI))
- mtk_pcie_enable_msi(port);
+ if (IS_ENABLED(CONFIG_PCI_MSI)) {
+ err = mtk_pcie_enable_msi(port);
+ if (err)
+ return err;
+ }
/* Set AHB to PCIe translation windows */
val = lower_32_bits(mem->start) |
--
2.18.0
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