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Date:   Wed, 6 Dec 2023 13:36:12 +0100
From:   Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>
To:     Jim Liu <jim.t90615@...il.com>, JJLIU0@...oton.com,
        krzysztof.kozlowski+dt@...aro.org, linus.walleij@...aro.org,
        andy@...nel.org, robh+dt@...nel.org, conor+dt@...nel.org,
        KWLIU@...oton.com
Cc:     linux-gpio@...r.kernel.org, devicetree@...r.kernel.org,
        linux-kernel@...r.kernel.org, openbmc@...ts.ozlabs.org
Subject: Re: [PATCH v8 3/3] gpio: nuvoton: Add Nuvoton NPCM sgpio driver

On 06/12/2023 02:45, Jim Liu wrote:
> Add Nuvoton BMC NPCM7xx/NPCM8xx sgpio driver support.
> Nuvoton NPCM SGPIO module is combine serial to parallel IC (HC595)
> and parallel to serial IC (HC165), and use APB3 clock to control it.
> This interface has 4 pins  (D_out , D_in, S_CLK, LDSH).
> BMC can use this driver to increase 64 GPI pins and 64 GPO pins to use.
> 
> Signed-off-by: Jim Liu <jim.t90615@...il.com>
> ---

...

> +	switch (reg) {
> +	case READ_DATA:
> +		return gpio->base + bank->rdata_reg;
> +	case WRITE_DATA:
> +		return gpio->base + bank->wdata_reg;
> +	case EVENT_CFG:
> +		return gpio->base + bank->event_config;
> +	case EVENT_STS:
> +		return gpio->base + bank->event_status;
> +	default:
> +		/* actually if code runs to here, it's an error case */
> +		dev_WARN(true, "Getting here is an error condition");

So you did not even compile your code. v8 and still not built :(

> +	}
> +	return 0;
> +}



Best regards,
Krzysztof

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