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Message-Id: <170196242582.12999.14639879842015285303.git-patchwork-notify@kernel.org>
Date:   Thu, 07 Dec 2023 15:20:25 +0000
From:   patchwork-bot+linux-riscv@...nel.org
To:     Clément Léger <cleger@...osinc.com>@ci.codeaurora.org
Cc:     linux-riscv@...ts.infradead.org, paul.walmsley@...ive.com,
        palmer@...belt.com, aou@...s.berkeley.edu,
        linux-kernel@...r.kernel.org
Subject: Re: [PATCH] riscv: fix misaligned access handling of C.SWSP and C.SDSP

Hello:

This patch was applied to riscv/linux.git (fixes)
by Palmer Dabbelt <palmer@...osinc.com>:

On Fri,  3 Nov 2023 10:02:23 +0100 you wrote:
> This is a backport of a fix that was done in OpenSBI: ec0559eb315b
> ("lib: sbi_misaligned_ldst: Fix handling of C.SWSP and C.SDSP").
> 
> Unlike C.LWSP/C.LDSP, these encodings can be used with the zero
> register, so checking that the rs2 field is non-zero is unnecessary.
> 
> Additionally, the previous check was incorrect since it was checking
> the immediate field of the instruction instead of the rs2 field.
> 
> [...]

Here is the summary with links:
  - riscv: fix misaligned access handling of C.SWSP and C.SDSP
    https://git.kernel.org/riscv/c/22e0eb04837a

You are awesome, thank you!
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