linux-kernel - Re: [PATCH net-next v1 3/3] net: dsa: microchip: Fix PHY loopback configuration for KSZ8794 and KSZ8873

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <20231207002823.2qx24nxjhn6e43w4@skbuf>
Date:   Thu, 7 Dec 2023 02:28:23 +0200
From:   Vladimir Oltean <olteanv@...il.com>
To:     Oleksij Rempel <o.rempel@...gutronix.de>
Cc:     "David S. Miller" <davem@...emloft.net>,
        Andrew Lunn <andrew@...n.ch>,
        Eric Dumazet <edumazet@...gle.com>,
        Florian Fainelli <f.fainelli@...il.com>,
        Jakub Kicinski <kuba@...nel.org>,
        Paolo Abeni <pabeni@...hat.com>,
        Woojung Huh <woojung.huh@...rochip.com>,
        Arun Ramadoss <arun.ramadoss@...rochip.com>,
        kernel@...gutronix.de, linux-kernel@...r.kernel.org,
        netdev@...r.kernel.org, UNGLinuxDriver@...rochip.com
Subject: Re: [PATCH net-next v1 3/3] net: dsa: microchip: Fix PHY loopback
 configuration for KSZ8794 and KSZ8873

On Tue, Nov 21, 2023 at 04:24:26PM +0100, Oleksij Rempel wrote:
> Correct the PHY loopback bit handling in the ksz8_w_phy_bmcr and
> ksz8_r_phy_bmcr functions for KSZ8794 and KSZ8873 variants in the ksz8795
> driver. Previously, the code erroneously used Bit 7 of port register 0xD
> for both chip variants, which is actually for LED configuration. This
> update ensures the correct registers and bits are used for the PHY
> loopback feature:
> 
> - For KSZ8794: Use 0xF / Bit 7.
> - For KSZ8873: Use 0xD / Bit 0.
> 
> Signed-off-by: Oleksij Rempel <o.rempel@...gutronix.de>
> ---

How did you find, and how did you test this, and on which one of the switches?

Opening the KSZ8873 datasheet, I am confused about their description of
the "far-end loopback". They make it sound as if this loops the packets
_received_ from the media side of PHY port A back to the transmit side
of PHY port A. But the route that these packets take is through the MAC
of PHY port A, then the switching fabric, then PHY port B which reflects
them back to PHY port A, where they finally egress.

Actually, they even go as far as saying that if you set the loopback bit
of port 1, the packets that will be looped back will be from port 2's
RXP/RXM to TXP/TXM pins, and viceversa.

If true, I believe this isn't the behavior expected by phy_loopback(),
where the TX signals from the media side of the PHY are looped back into
the RX side.