linux-kernel - RE: [PATCH 1/2] dt-bindings: phy: realtek: Add Realtek DHC RTD SoC PCIe PHY

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <951a35ee5bb84ac4bf2462729909fe7c@realtek.com>
Date:   Thu, 7 Dec 2023 10:09:16 +0000
From:   TY_Chang[張子逸] <tychang@...ltek.com>
To:     Conor Dooley <conor@...nel.org>
CC:     Vinod Koul <vkoul@...nel.org>,
        Kishon Vijay Abraham I <kishon@...nel.org>,
        Rob Herring <robh+dt@...nel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
        Conor Dooley <conor+dt@...nel.org>,
        "linux-phy@...ts.infradead.org" <linux-phy@...ts.infradead.org>,
        "devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        Stanley Chang[昌育德] <stanley_chang@...ltek.com>
Subject: RE: [PATCH 1/2] dt-bindings: phy: realtek: Add Realtek DHC RTD SoC PCIe PHY


Hi Conor,

Thank you for the review.

>> +properties:
>> +  compatible:
>> +    enum:
>
>> +      - realtek,rtd1319-pcie0-phy
>> +      - realtek,rtd1319-pcie1-phy
>> +      - realtek,rtd1319-pcie2-phy
>> +      - realtek,rtd1619b-pcie1-phy
>> +      - realtek,rtd1619b-pcie2-phy
>
>Please explain why different PHYs on the same SoC need different compatibles.
>

I hadn't thought this clearly. I added the compatible for each PCIe ports. However,
only one compatible is needed for the PHY driver on each SoC.
I will revise it in the next version.

There are multiple ports for PCIe on different SoCs. RTD1319 has three PCIe ports (port 0, port1, port2).
RTD1619B has two PCIe ports. Both RTD1319D and RTD1315E have one PCIe port.

>> +      - realtek,rtd1319d-pcie1-phy
>> +      - realtek,rtd1315e-pcie1-phy
>
>And why bother with the 1 here given there is no 0 or 2?
>

I'm sorry for the confusion caused by the naming. The PCIe controller register address on 
RTD1319D and RTD1315E is the same as RTD1319's PCIe port1, so I named it as pcie1.
I'll refrain from using such naming in the future.

>This looks suspiciously like abuse of the compatible - especially since most of
>the ops are the same despite the differing compatibles. The case where that
>does not apply, it looks like the issue is down to the portion of the nvmem cell
>corresponding to the PHY, which has nothing to do with the programming model
>of the PHY itself IMO.

Thanks,
Tzuyi Chang