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Message-ID: <CAJM55Z831ucY4QqPTR_0zJVB05UUT4W-3M0CGzvtyPo=AMD=Vw@mail.gmail.com>
Date:   Fri, 8 Dec 2023 08:05:31 -0800
From:   Emil Renner Berthing <emil.renner.berthing@...onical.com>
To:     Sia Jee Heng <jeeheng.sia@...rfivetech.com>, kernel@...il.dk,
        robh+dt@...nel.org, krzysztof.kozlowski+dt@...aro.org,
        krzk@...nel.org, conor+dt@...nel.org, paul.walmsley@...ive.com,
        palmer@...belt.com, aou@...s.berkeley.edu,
        daniel.lezcano@...aro.org, tglx@...utronix.de, conor@...nel.org,
        anup@...infault.org, gregkh@...uxfoundation.org,
        jirislaby@...nel.org, michal.simek@....com,
        michael.zhu@...rfivetech.com, drew@...gleboard.org
Cc:     devicetree@...r.kernel.org, linux-riscv@...ts.infradead.org,
        linux-kernel@...r.kernel.org, leyfoon.tan@...rfivetech.com
Subject: Re: [PATCH v3 6/6] riscv: dts: starfive: Add initial StarFive JH8100
 device tree

Sia Jee Heng wrote:
> Add initial device tree for the StarFive JH8100 RISC-V SoC.
>
> Signed-off-by: Sia Jee Heng <jeeheng.sia@...rfivetech.com>
> Reviewed-by: Ley Foon Tan <leyfoon.tan@...rfivetech.com>

Looks good to me, thanks.

Acked-by: Emil Renner Berthing <emil.renner.berthing@...onical.com>

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