linux-kernel - [PATCH v4 01/22] MIPS: compressed: Use correct instruction for 64 bit code

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Message-ID: <20231208161249.1827174-2-gregory.clement@bootlin.com>
Date:   Fri,  8 Dec 2023 17:12:17 +0100
From:   Gregory CLEMENT <gregory.clement@...tlin.com>
To:     Paul Burton <paulburton@...nel.org>,
        Thomas Bogendoerfer <tsbogend@...ha.franken.de>,
        linux-mips@...r.kernel.org, Jiaxun Yang <jiaxun.yang@...goat.com>,
        Rob Herring <robh+dt@...nel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
        devicetree@...r.kernel.org, linux-kernel@...r.kernel.org
Cc:     Vladimir Kondratiev <vladimir.kondratiev@...ileye.com>,
        Tawfik Bayouk <tawfik.bayouk@...ileye.com>,
        Alexandre Belloni <alexandre.belloni@...tlin.com>,
        Théo Lebrun <theo.lebrun@...tlin.com>,
        Thomas Petazzoni <thomas.petazzoni@...tlin.com>,
        Gregory CLEMENT <gregory.clement@...tlin.com>,
        Philippe Mathieu-Daudé <philmd@...aro.org>,
        Florian Fainelli <florian.fainelli@...adcom.com>
Subject: [PATCH v4 01/22] MIPS: compressed: Use correct instruction for 64 bit code

The code clearing BSS already use macro or use correct instruction
depending if the CPU is 32 bits or 64 bits. However, a few
instructions remained 32 bits only.

By using the accurate MACRO, it is now possible to deal with memory
address beyond 32 bits. As a side effect, when using 64bits processor,
it also divides the loop number needed to clear the BSS by 2.

Reviewed-by: Philippe Mathieu-Daudé <philmd@...aro.org>
Reviewed-by: Florian Fainelli <florian.fainelli@...adcom.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@...tlin.com>
---
 arch/mips/boot/compressed/head.S | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/mips/boot/compressed/head.S b/arch/mips/boot/compressed/head.S
index 5795d0af1e1b2..d237a834b85ee 100644
--- a/arch/mips/boot/compressed/head.S
+++ b/arch/mips/boot/compressed/head.S
@@ -25,8 +25,8 @@
 	/* Clear BSS */
 	PTR_LA	a0, _edata
 	PTR_LA	a2, _end
-1:	sw	zero, 0(a0)
-	addiu	a0, a0, 4
+1:	PTR_S	zero, 0(a0)
+	PTR_ADDIU a0, a0, PTRSIZE
 	bne	a2, a0, 1b
 
 	PTR_LA	a0, (.heap)	     /* heap address */
-- 
2.42.0