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Message-ID: <87fs0csqu1.ffs@tglx>
Date:   Fri, 08 Dec 2023 15:37:26 +0100
From:   Thomas Gleixner <tglx@...utronix.de>
To:     Konrad Dybcio <konrad.dybcio@...aro.org>,
        Andy Gross <agross@...nel.org>,
        Bjorn Andersson <andersson@...nel.org>,
        Marc Zyngier <maz@...nel.org>,
        Rob Herring <robh+dt@...nel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
        Shawn Guo <shawn.guo@...aro.org>,
        Conor Dooley <conor+dt@...nel.org>
Cc:     Marijn Suijten <marijn.suijten@...ainline.org>,
        linux-arm-msm@...r.kernel.org, linux-kernel@...r.kernel.org,
        devicetree@...r.kernel.org,
        Konrad Dybcio <konrad.dybcio@...aro.org>,
        Bryan O'Donoghue <bryan.odonoghue@...aro.org>
Subject: Re: [PATCH v7 2/2] irqchip: irq-qcom-mpm: Support passing a slice
 of SRAM as reg space

On Mon, Nov 27 2023 at 16:52, Konrad Dybcio wrote:

The prefix in the subject is wrong. Also please write out register. This
is not Xitter.

> The MPM hardware is accessible to us from the ARM CPUs through a shared

to us? Can you access that hardware? I doubt it.

Please use neutral tone as documented in Documentation/process/

> memory region (RPM MSG RAM) that's also concurrently accessed by other
> kinds of cores on the system (like modem, ADSP etc.). Modeling this
> relation in a (somewhat) sane manner in the device tree basically
> requires us to either present the MPM as a child of said memory region
> (which makes little sense, as a mapped memory carveout is not a bus),
> define nodes which bleed their register spaces into one another, or
> passing their slice of the MSG RAM through some kind of a property.
>
> Go with the third option and add a way to map a region passed through
> the "qcom,rpm-msg-ram" property as our register space.
>
> The current way of using 'reg' is preserved for ABI reasons.

It's not an ABI reason. It's backwards compatibility with old device
trees, right?

I'll fix it up for you this time. No need to resend.

Thanks,

        tglx

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