linux-kernel - Re: [PATCH RFC 02/13] x86: Add a Kconfig option for posted MSI

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Date:   Sat, 9 Dec 2023 13:24:46 -0800
From:   Jacob Pan <jacob.jun.pan@...ux.intel.com>
To:     Thomas Gleixner <tglx@...utronix.de>
Cc:     LKML <linux-kernel@...r.kernel.org>, X86 Kernel <x86@...nel.org>,
        iommu@...ts.linux.dev, Lu Baolu <baolu.lu@...ux.intel.com>,
        kvm@...r.kernel.org, Dave Hansen <dave.hansen@...el.com>,
        Joerg Roedel <joro@...tes.org>,
        "H. Peter Anvin" <hpa@...or.com>, Borislav Petkov <bp@...en8.de>,
        Ingo Molnar <mingo@...hat.com>,
        Raj Ashok <ashok.raj@...el.com>,
        "Tian, Kevin" <kevin.tian@...el.com>, maz@...nel.org,
        peterz@...radead.org, seanjc@...gle.com,
        Robin Murphy <robin.murphy@....com>,
        jacob.jun.pan@...ux.intel.com
Subject: Re: [PATCH RFC 02/13] x86: Add a Kconfig option for posted MSI

Hi Thomas,

On Wed, 06 Dec 2023 17:35:29 +0100, Thomas Gleixner <tglx@...utronix.de>
wrote:

> On Sat, Nov 11 2023 at 20:16, Jacob Pan wrote:
> > This option will be used to support delivering MSIs as posted
> > interrupts. Interrupt remapping is required.  
> 
> The last sentence does not make sense.
will remove, superfluous statement.

> > Signed-off-by: Jacob Pan <jacob.jun.pan@...ux.intel.com>
> > ---
> >  arch/x86/Kconfig | 10 ++++++++++
> >  1 file changed, 10 insertions(+)
> >
> > diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
> > index 66bfabae8814..f16882ddb390 100644
> > --- a/arch/x86/Kconfig
> > +++ b/arch/x86/Kconfig
> > @@ -463,6 +463,16 @@ config X86_X2APIC
> >  
> >  	  If you don't know what to do here, say N.
> >  
> > +config X86_POSTED_MSI
> > +	bool "Enable MSI and MSI-x delivery by posted interrupts"
> > +	depends on X86_X2APIC && X86_64 && IRQ_REMAP
> > +	help
> > +	  This enables MSIs that are under IRQ remapping to be
> > delivered as posted  
> 
> s/IRQ/interrupt/
OK, will replace this and IRQs below.

> This is text and not Xitter.
> 
> 
> > +	  interrupts to the host kernel. IRQ throughput can
> > potentially be improved
> > +	  by coalescing CPU notifications during high frequency IRQ
> > bursts. +
> > +	  If you don't know what to do here, say N.
> > +
> >  config X86_MPPARSE
> >  	bool "Enable MPS table" if ACPI
> >  	default y  


Thanks,

Jacob