| lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC | |
|
Open Source and information security mailing list archives
| ||
|
Message-ID: <421ede4c-7a96-47e0-9b82-0eb350b59c33@linaro.org>
Date: Sun, 10 Dec 2023 14:00:42 +0100
From: Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>
To: Jaewon Kim <jaewon02.kim@...sung.com>,
Alim Akhtar <alim.akhtar@...sung.com>,
Rob Herring <robh+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>,
Tomasz Figa <tomasz.figa@...il.com>,
Sylwester Nawrocki <s.nawrocki@...sung.com>,
Linus Walleij <linus.walleij@...aro.org>,
Thierry Reding <thierry.reding@...il.com>,
Uwe Kleine-K?nig <u.kleine-koenig@...gutronix.de>,
Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
Jiri Slaby <jirislaby@...nel.org>
Cc: linux-arm-kernel@...ts.infradead.org,
linux-samsung-soc@...r.kernel.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org, linux-gpio@...r.kernel.org,
linux-pwm@...r.kernel.org, linux-serial@...r.kernel.org
Subject: Re: [PATCH v3 3/4] pinctrl: samsung: support ExynosAuto GPIO
structure
On 08/12/2023 08:45, Jaewon Kim wrote:
> New ExynosAuto series GPIO have a different register structure.
> In the existing Exynos series, EINT control register enumerated after
> a specific offset (e.g EXYNOS_GPIO_ECON_OFFSET, EXYNOS_GPIO_EMASK_OFFSET).
> However, from ExynosAutov920 SoC, the register that controls EINT belongs
> to each GPIO bank, and each GPIO bank has 0x1000 align.
>
> This is a structure to protect the GPIO bank using S2MPU in VM environment,
> and will only be applied in ExynosAuto series SoCs.
>
> -------------------------------------------------
> | original | ExynosAutov920 |
> |-----------------------------------------------|
> | 0x0 GPIO_CON | 0x0 GPIO_CON |
> | 0x4 GPIO_DAT | 0x4 GPIO_DAT |
> | 0x8 GPIO_PUD | 0x8 GPIO_PUD |
> | 0xc GPIO_DRV | 0xc GPIO_DRV |
> | 0x10 GPIO_CONPDN | 0x10 GPIO_CONPDN |
> | 0x14 GPIO_PUDPDN | 0x14 GPIO_PUDPDN |
> | 0x700 EINT_CON | 0x18 EINT_CON |
> | 0x800 EINT_FLTCON | 0x1c EINT_FLTCON0 |
> | 0x900 EINT_MASK | 0x20 EINT_FLTCON1 |
> | 0xa00 EINT_PEND | 0x24 EINT_MASK |
> | | 0x28 EINT_PEND |
> -------------------------------------------------
>
> Signed-off-by: Jaewon Kim <jaewon02.kim@...sung.com>
> ---
> drivers/pinctrl/samsung/pinctrl-exynos.c | 81 +++++++++++++++++++++--
> drivers/pinctrl/samsung/pinctrl-exynos.h | 1 +
> drivers/pinctrl/samsung/pinctrl-samsung.c | 3 +
> drivers/pinctrl/samsung/pinctrl-samsung.h | 12 ++++
> 4 files changed, 90 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/pinctrl/samsung/pinctrl-exynos.c b/drivers/pinctrl/samsung/pinctrl-exynos.c
> index 6b58ec84e34b..f798f64b1122 100644
> --- a/drivers/pinctrl/samsung/pinctrl-exynos.c
> +++ b/drivers/pinctrl/samsung/pinctrl-exynos.c
> @@ -56,6 +56,9 @@ static void exynos_irq_mask(struct irq_data *irqd)
> unsigned int mask;
> unsigned long flags;
>
> + if (bank->eint_mask_offset)
> + reg_mask = bank->pctl_offset + bank->eint_mask_offset;
Drop the initialization of reg_mask so:
else:
reg_mask = ...
> +
> raw_spin_lock_irqsave(&bank->slock, flags);
>
> mask = readl(bank->eint_base + reg_mask);
> @@ -72,6 +75,9 @@ static void exynos_irq_ack(struct irq_data *irqd)
> struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd);
> unsigned long reg_pend = our_chip->eint_pend + bank->eint_offset;
>
> + if (bank->eint_pend_offset)
> + reg_pend = bank->pctl_offset + bank->eint_pend_offset;
> +
> writel(1 << irqd->hwirq, bank->eint_base + reg_pend);
> }
>
> @@ -95,6 +101,9 @@ static void exynos_irq_unmask(struct irq_data *irqd)
> if (irqd_get_trigger_type(irqd) & IRQ_TYPE_LEVEL_MASK)
> exynos_irq_ack(irqd);
>
Ditto
> + if (bank->eint_mask_offset)
> + reg_mask = bank->pctl_offset + bank->eint_mask_offset;
> +
> raw_spin_lock_irqsave(&bank->slock, flags);
>
> mask = readl(bank->eint_base + reg_mask);
> @@ -139,6 +148,9 @@ static int exynos_irq_set_type(struct irq_data *irqd, unsigned int type)
> else
> irq_set_handler_locked(irqd, handle_level_irq);
>
Ditto
> + if (bank->eint_con_offset)
> + reg_con = bank->pctl_offset + bank->eint_con_offset;
> +
> con = readl(bank->eint_base + reg_con);
> con &= ~(EXYNOS_EINT_CON_MASK << shift);
> con |= trig_type << shift;
> @@ -221,6 +233,18 @@ static const struct exynos_irq_chip exynos_gpio_irq_chip __initconst = {
> /* eint_wake_mask_value not used */
> };
>
> +static const struct exynos_irq_chip exynosauto_gpio_irq_chip __initconst = {
No related to this patch.
> + .chip = {
> + .name = "exynosauto_gpio_irq_chip",
> + .irq_unmask = exynos_irq_unmask,
> + .irq_mask = exynos_irq_mask,
> + .irq_ack = exynos_irq_ack,
> + .irq_set_type = exynos_irq_set_type,
> + .irq_request_resources = exynos_irq_request_resources,
> + .irq_release_resources = exynos_irq_release_resources,
> + },
> +};
> +
> static int exynos_eint_irq_map(struct irq_domain *h, unsigned int virq,
> irq_hw_number_t hw)
> {
> @@ -247,7 +271,10 @@ static irqreturn_t exynos_eint_gpio_irq(int irq, void *data)
> unsigned int svc, group, pin;
> int ret;
>
> - svc = readl(bank->eint_base + EXYNOS_SVC_OFFSET);
> + if (bank->eint_con_offset)
> + svc = readl(bank->eint_base + EXYNOSAUTO_SVC_OFFSET);
This belongs to the second patch. The point of this patch is only to
customize the offsets. There should be nothing autov920 here.
> + else
> + svc = readl(bank->eint_base + EXYNOS_SVC_OFFSET);
> group = EXYNOS_SVC_GROUP(svc);
> pin = svc & EXYNOS_SVC_NUM_MASK;
>
> @@ -297,8 +324,12 @@ __init int exynos_eint_gpio_init(struct samsung_pinctrl_drv_data *d)
> if (bank->eint_type != EINT_TYPE_GPIO)
> continue;
>
> - bank->irq_chip = devm_kmemdup(dev, &exynos_gpio_irq_chip,
> - sizeof(*bank->irq_chip), GFP_KERNEL);
> + if (bank->eint_con_offset)
> + bank->irq_chip = devm_kmemdup(dev, &exynosauto_gpio_irq_chip,
> + sizeof(*bank->irq_chip), GFP_KERNEL);
> + else
> + bank->irq_chip = devm_kmemdup(dev, &exynos_gpio_irq_chip,
> + sizeof(*bank->irq_chip), GFP_KERNEL);
> if (!bank->irq_chip) {
> ret = -ENOMEM;
> goto err_domains;
> @@ -655,6 +686,19 @@ static void exynos_pinctrl_suspend_bank(
> pr_debug("%s: save mask %#010x\n", bank->name, save->eint_mask);
> }
>
> +static void exynosauto_pinctrl_suspend_bank(struct samsung_pinctrl_drv_data *drvdata,
> + struct samsung_pin_bank *bank)
> +{
> + struct exynos_eint_gpio_save *save = bank->soc_priv;
> + void __iomem *regs = bank->eint_base;
> +
> + save->eint_con = readl(regs + bank->pctl_offset + bank->eint_con_offset);
> + save->eint_mask = readl(regs + bank->pctl_offset + bank->eint_mask_offset);
> +
> + pr_debug("%s: save con %#010x\n", bank->name, save->eint_con);
> + pr_debug("%s: save mask %#010x\n", bank->name, save->eint_mask);
> +}
> +
> void exynos_pinctrl_suspend(struct samsung_pinctrl_drv_data *drvdata)
> {
> struct samsung_pin_bank *bank = drvdata->pin_banks;
> @@ -662,8 +706,12 @@ void exynos_pinctrl_suspend(struct samsung_pinctrl_drv_data *drvdata)
> int i;
>
> for (i = 0; i < drvdata->nr_banks; ++i, ++bank) {
> - if (bank->eint_type == EINT_TYPE_GPIO)
> - exynos_pinctrl_suspend_bank(drvdata, bank);
> + if (bank->eint_type == EINT_TYPE_GPIO) {
> + if (bank->eint_con_offset)
> + exynosauto_pinctrl_suspend_bank(drvdata, bank);
> + else
> + exynos_pinctrl_suspend_bank(drvdata, bank);
> + }
> else if (bank->eint_type == EINT_TYPE_WKUP) {
> if (!irq_chip) {
> irq_chip = bank->irq_chip;
> @@ -704,14 +752,33 @@ static void exynos_pinctrl_resume_bank(
> + bank->eint_offset);
> }
>
> +static void exynosauto_pinctrl_resume_bank(struct samsung_pinctrl_drv_data *drvdata,
> + struct samsung_pin_bank *bank)
> +{
> + struct exynos_eint_gpio_save *save = bank->soc_priv;
> + void __iomem *regs = bank->eint_base;
> +
> + pr_debug("%s: con %#010x => %#010x\n", bank->name,
> + readl(regs + bank->pctl_offset + bank->eint_con_offset), save->eint_con);
> + pr_debug("%s: mask %#010x => %#010x\n", bank->name,
> + readl(regs + bank->pctl_offset + bank->eint_mask_offset), save->eint_mask);
> +
> + writel(save->eint_con, regs + bank->pctl_offset + bank->eint_con_offset);
> + writel(save->eint_mask, regs + bank->pctl_offset + bank->eint_mask_offset);
> +}
> +
> void exynos_pinctrl_resume(struct samsung_pinctrl_drv_data *drvdata)
> {
> struct samsung_pin_bank *bank = drvdata->pin_banks;
> int i;
>
> for (i = 0; i < drvdata->nr_banks; ++i, ++bank)
> - if (bank->eint_type == EINT_TYPE_GPIO)
> - exynos_pinctrl_resume_bank(drvdata, bank);
> + if (bank->eint_type == EINT_TYPE_GPIO) {
> + if (bank->eint_con_offset)
> + exynosauto_pinctrl_resume_bank(drvdata, bank);
> + else
> + exynos_pinctrl_resume_bank(drvdata, bank);
> + }
> }
>
> static void exynos_retention_enable(struct samsung_pinctrl_drv_data *drvdata)
> diff --git a/drivers/pinctrl/samsung/pinctrl-exynos.h b/drivers/pinctrl/samsung/pinctrl-exynos.h
> index 3ac52c2cf998..5049c170e958 100644
> --- a/drivers/pinctrl/samsung/pinctrl-exynos.h
> +++ b/drivers/pinctrl/samsung/pinctrl-exynos.h
> @@ -31,6 +31,7 @@
> #define EXYNOS7_WKUP_EMASK_OFFSET 0x900
> #define EXYNOS7_WKUP_EPEND_OFFSET 0xA00
> #define EXYNOS_SVC_OFFSET 0xB08
> +#define EXYNOSAUTO_SVC_OFFSET 0xF008
As well not related to this patch.
Best regards,
Krzysztof
Powered by blists - more mailing lists