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Message-ID: <CAHP4M8WQdQfjxa-oqGTEF-kfF3j8En6V5fi7gyNbGegwFqfpCQ@mail.gmail.com>
Date: Mon, 11 Dec 2023 18:36:26 +0530
From: Ajay Garg <ajaygargnsit@...il.com>
To: linux-arm-kernel@...ts.infradead.org,
Linux Kernel Mailing List <linux-kernel@...r.kernel.org>
Subject: Query on a rare simultaneous processing of interrupts from GIC/NVIC
Hi everyone.
Let's say the following code is shared by multiple ISRs :
spin_lock_irqsave
<critical section>
spin_lock_irqrestore
Also, following sequencing happens :
*
Low-priority interrupt comes in, and GIC/NVIC causes it jump to ISR.
*
Low-priority interrupt starts executing "spin_lock_irqsave".
*
Before preemption and interrupts could be disabled (by the executing
low-priority interrupt). high-priority interrupt comes in.
Since a higher priority interrupt has come in, the GIC/NVIC causes it
to start executing the "spin_lock_irqsave" statement.
*
Through the low-priority interrupt executing, "spin_lock_irqsave" has completed.
Preemption and interrupts are disabled, and low-priority interrupt
grabs the spin lock.
*
High-priority interrupt spins on the spin-lock.
Is the above sequencing possible?
In other words, although the first interrupt did its best to disable
all preemption and interrupts before it could enter the critical
section, yet above sequencing *will* cause the high-priority interrupt
to spin?
Many thanks in advance for your time for help !
Thanks and Regards,
Ajay
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