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Message-ID: <20231212130116.848530-3-haxel@fzi.de>
Date: Tue, 12 Dec 2023 14:01:13 +0100
From: Frederik Haxel <haxel@....de>
To: unlisted-recipients:; (no To-header on input)
CC: Vitaly Wool <vitaly.wool@...sulko.com>,
Frederik Haxel <haxel@....de>,
Paul Walmsley <paul.walmsley@...ive.com>,
Palmer Dabbelt <palmer@...belt.com>,
Albert Ou <aou@...s.berkeley.edu>,
Andy Chiu <andy.chiu@...ive.com>,
Heiko Stuebner <heiko@...ech.de>,
Greentime Hu <greentime.hu@...ive.com>,
Conor Dooley <conor.dooley@...rochip.com>,
"Sami Tolvanen" <samitolvanen@...gle.com>,
Clément Léger <cleger@...osinc.com>,
Nam Cao <namcaov@...il.com>, Guo Ren <guoren@...nel.org>,
Alexandre Ghiti <alexghiti@...osinc.com>,
Andrew Jones <ajones@...tanamicro.com>,
Björn Töpel <bjorn@...osinc.com>,
Baoquan He <bhe@...hat.com>,
Chen Jiahao <chenjiahao16@...wei.com>,
<linux-riscv@...ts.infradead.org>, <linux-kernel@...r.kernel.org>
Subject: [PATCH 2/3] riscv: Fixed wrong register in XIP_FIXUP_FLASH_OFFSET macro
During the refactoring, a bug was introduced in the rarly used
XIP_FIXUP_FLASH_OFFSET macro.
Fixes: bee7fbc38579 ("RISC-V CPU Idle Support")
Fixes: e7681beba992 ("RISC-V: Split out the XIP fixups into their own file")
Signed-off-by: Frederik Haxel <haxel@....de>
---
arch/riscv/include/asm/xip_fixup.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/riscv/include/asm/xip_fixup.h b/arch/riscv/include/asm/xip_fixup.h
index d4ffc3c37649..b65bf6306f69 100644
--- a/arch/riscv/include/asm/xip_fixup.h
+++ b/arch/riscv/include/asm/xip_fixup.h
@@ -13,7 +13,7 @@
add \reg, \reg, t0
.endm
.macro XIP_FIXUP_FLASH_OFFSET reg
- la t1, __data_loc
+ la t0, __data_loc
REG_L t1, _xip_phys_offset
sub \reg, \reg, t1
add \reg, \reg, t0
--
2.34.1
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