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Message-ID: <ZXnRcfuvQBo6UDCx@APC323>
Date: Wed, 13 Dec 2023 23:44:49 +0800
From: Yu-Chien Peter Lin <peterlin@...estech.com>
To: Anup Patel <apatel@...tanamicro.com>
CC: <acme@...nel.org>, <adrian.hunter@...el.com>,
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Subject: Re: [PATCH v5 03/16] irqchip/riscv-intc: Introduce Andes hart-level
interrupt controller
On Wed, Dec 13, 2023 at 08:15:28PM +0530, Anup Patel wrote:
> On Wed, Dec 13, 2023 at 12:35 PM Yu Chien Peter Lin
> <peterlin@...estech.com> wrote:
> >
> > Add support for the Andes hart-level interrupt controller. This
> > controller provides interrupt mask/unmask functions to access the
> > custom register (SLIE) where the non-standard S-mode local interrupt
> > enable bits are located.
> >
> > To share the riscv_intc_domain_map() with the generic RISC-V INTC and
> > ACPI, add a chip parameter to riscv_intc_init_common(), so it can be
> > passed to the irq_domain_set_info() as private data.
> >
> > Andes hart-level interrupt controller requires the "andestech,cpu-intc"
> > compatible string to be present in interrupt-controller of cpu node.
> > e.g.,
> >
> > cpu0: cpu@0 {
> > compatible = "andestech,ax45mp", "riscv";
> > ...
> > cpu0-intc: interrupt-controller {
> > #interrupt-cells = <0x01>;
> > compatible = "andestech,cpu-intc", "riscv,cpu-intc";
> > interrupt-controller;
> > };
> > };
> >
> > Signed-off-by: Yu Chien Peter Lin <peterlin@...estech.com>
> > Reviewed-by: Charles Ci-Jyun Wu <dminus@...estech.com>
> > Reviewed-by: Leo Yu-Chi Liang <ycliang@...estech.com>
> > ---
> > Changes v1 -> v2:
> > - New patch
> > Changes v2 -> v3:
> > - Return -ENXIO if no valid compatible INTC found
> > - Allow falling back to generic RISC-V INTC
> > Changes v3 -> v4: (Suggested by Thomas [1])
> > - Add comment to andes irq chip function
> > - Refine code flow to share with generic RISC-V INTC and ACPI
> > - Move Andes specific definitions to include/linux/soc/andes/irq.h
> > Changes v4 -> v5: (Suggested by Thomas)
> > - Fix commit message
> > - Subtract ANDES_SLI_CAUSE_BASE from d->hwirq to calculate the value of mask
> > - Do not set chip_data to the chip itself with irq_domain_set_info()
> > - Follow reverse fir tree order variable declarations
> >
> > [1] https://patchwork.kernel.org/project/linux-riscv/patch/20231019135723.3657156-1-peterlin@andestech.com/
> > ---
> > drivers/irqchip/irq-riscv-intc.c | 53 ++++++++++++++++++++++++++++----
> > include/linux/soc/andes/irq.h | 17 ++++++++++
> > 2 files changed, 64 insertions(+), 6 deletions(-)
> > create mode 100644 include/linux/soc/andes/irq.h
> >
> > diff --git a/drivers/irqchip/irq-riscv-intc.c b/drivers/irqchip/irq-riscv-intc.c
> > index 2fdd40f2a791..0b6bf3fb1dba 100644
> > --- a/drivers/irqchip/irq-riscv-intc.c
> > +++ b/drivers/irqchip/irq-riscv-intc.c
> > @@ -17,6 +17,7 @@
> > #include <linux/module.h>
> > #include <linux/of.h>
> > #include <linux/smp.h>
> > +#include <linux/soc/andes/irq.h>
> >
> > static struct irq_domain *intc_domain;
> >
> > @@ -46,6 +47,31 @@ static void riscv_intc_irq_unmask(struct irq_data *d)
> > csr_set(CSR_IE, BIT(d->hwirq));
> > }
> >
> > +static void andes_intc_irq_mask(struct irq_data *d)
> > +{
> > + /*
> > + * Andes specific S-mode local interrupt causes (hwirq)
> > + * are defined as (256 + n) and controlled by n-th bit
> > + * of SLIE.
> > + */
> > + unsigned int mask = BIT(d->hwirq - ANDES_SLI_CAUSE_BASE);
> > +
> > + if (d->hwirq < ANDES_SLI_CAUSE_BASE)
> > + csr_clear(CSR_IE, mask);
> > + else
> > + csr_clear(ANDES_CSR_SLIE, mask);
> > +}
> > +
> > +static void andes_intc_irq_unmask(struct irq_data *d)
> > +{
> > + unsigned int mask = BIT(d->hwirq - ANDES_SLI_CAUSE_BASE);
> > +
> > + if (d->hwirq < ANDES_SLI_CAUSE_BASE)
> > + csr_set(CSR_IE, mask);
> > + else
> > + csr_set(ANDES_CSR_SLIE, mask);
>
> Clearly, Andes does not have any CSR for:
> XLEN <= local interrupt <ANDES_SLI_CAUSE_BASE
> and
> ANDES_SLI_CAUSE_BASE + XLEN <= local interrupt
Ah, what am I doing here.
sorry for that silly patch.
Regards,
Peter Lin
> Regards,
> Anup
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