linux-kernel - RE: [PATCH v3 2/6] dt-bindings: riscv: Add StarFive JH8100 SoC

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Message-ID: <84b808cb028c40a29c9f81011931afba@EXMBX061.cuchost.com>
Date:   Wed, 13 Dec 2023 13:24:23 +0000
From:   Leyfoon Tan <leyfoon.tan@...rfivetech.com>
To:     Conor Dooley <conor@...nel.org>,
        JeeHeng Sia <jeeheng.sia@...rfivetech.com>
CC:     "kernel@...il.dk" <kernel@...il.dk>,
        "robh+dt@...nel.org" <robh+dt@...nel.org>,
        "krzysztof.kozlowski+dt@...aro.org" 
        <krzysztof.kozlowski+dt@...aro.org>,
        "krzk@...nel.org" <krzk@...nel.org>,
        "conor+dt@...nel.org" <conor+dt@...nel.org>,
        "paul.walmsley@...ive.com" <paul.walmsley@...ive.com>,
        "palmer@...belt.com" <palmer@...belt.com>,
        "aou@...s.berkeley.edu" <aou@...s.berkeley.edu>,
        "daniel.lezcano@...aro.org" <daniel.lezcano@...aro.org>,
        "tglx@...utronix.de" <tglx@...utronix.de>,
        "anup@...infault.org" <anup@...infault.org>,
        "gregkh@...uxfoundation.org" <gregkh@...uxfoundation.org>,
        "jirislaby@...nel.org" <jirislaby@...nel.org>,
        "michal.simek@....com" <michal.simek@....com>,
        Michael Zhu <michael.zhu@...rfivetech.com>,
        "drew@...gleboard.org" <drew@...gleboard.org>,
        "devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
        "linux-riscv@...ts.infradead.org" <linux-riscv@...ts.infradead.org>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        Conor Dooley <conor.dooley@...rochip.com>
Subject: RE: [PATCH v3 2/6] dt-bindings: riscv: Add StarFive JH8100 SoC



> -----Original Message-----
> From: Conor Dooley <conor@...nel.org>
> Sent: Wednesday, December 13, 2023 8:43 PM
> To: JeeHeng Sia <jeeheng.sia@...rfivetech.com>
> Cc: kernel@...il.dk; robh+dt@...nel.org; krzysztof.kozlowski+dt@...aro.org;
> krzk@...nel.org; conor+dt@...nel.org; paul.walmsley@...ive.com;
> palmer@...belt.com; aou@...s.berkeley.edu; daniel.lezcano@...aro.org;
> tglx@...utronix.de; anup@...infault.org; gregkh@...uxfoundation.org;
> jirislaby@...nel.org; michal.simek@....com; Michael Zhu
> <michael.zhu@...rfivetech.com>; drew@...gleboard.org;
> devicetree@...r.kernel.org; linux-riscv@...ts.infradead.org; linux-
> kernel@...r.kernel.org; Leyfoon Tan <leyfoon.tan@...rfivetech.com>; Conor
> Dooley <conor.dooley@...rochip.com>
> Subject: Re: [PATCH v3 2/6] dt-bindings: riscv: Add StarFive JH8100 SoC
> 
> On Fri, Dec 01, 2023 at 08:14:06PM +0800, Sia Jee Heng wrote:
> > Add device tree bindings for the StarFive JH8100 RISC-V SoC.
> >
> > Signed-off-by: Sia Jee Heng <jeeheng.sia@...rfivetech.com>
> > Reviewed-by: Ley Foon Tan <leyfoon.tan@...rfivetech.com>
> > Acked-by: Conor Dooley <conor.dooley@...rochip.com>
> > ---
> >  Documentation/devicetree/bindings/riscv/starfive.yaml | 4 ++++
> >  1 file changed, 4 insertions(+)
> >
> > diff --git a/Documentation/devicetree/bindings/riscv/starfive.yaml
> > b/Documentation/devicetree/bindings/riscv/starfive.yaml
> > index cc4d92f0a1bf..12d7844232b8 100644
> > --- a/Documentation/devicetree/bindings/riscv/starfive.yaml
> > +++ b/Documentation/devicetree/bindings/riscv/starfive.yaml
> > @@ -30,6 +30,10 @@ properties:
> >                - starfive,visionfive-2-v1.3b
> >            - const: starfive,jh7110
> >
> > +      - items:
> > +          - enum:
> > +              - starfive,jh8100-evb
> 
> Hmm, reading some of the other threads it appears that the evaluation
> platform that you guys have is actually just an FPGA? Could you please provide
> more information as to what this "evb" actually is?
> 
> If it is just an FPGA-based evaluation platform I don't think that we want to
> merge patches for the platform. I'm fine with patches adding peripheral
> support, but the soc/board dts files and things like pinctrl or clock drivers I am
> not keen on.
> Perhaps Emil also has an opinion on this.
> 
> Thanks,
> Conor.

We have been testing on the FPGA/emulator for pre-silicon validation. It will have real silicon SoC next year.

Regards
Ley Foon