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Message-Id: <20231215-x1e80100-dts-missing-nodes-v2-0-5a6efc04d00c@linaro.org>
Date: Fri, 15 Dec 2023 00:35:36 +0200
From: Abel Vesa <abel.vesa@...aro.org>
To: Andy Gross <agross@...nel.org>, Bjorn Andersson <andersson@...nel.org>,
Konrad Dybcio <konrad.dybcio@...aro.org>, Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Conor Dooley <conor+dt@...nel.org>
Cc: linux-arm-msm@...r.kernel.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org, Abel Vesa <abel.vesa@...aro.org>,
Rajendra Nayak <quic_rjendra@...cinc.com>,
Sibi Sankar <quic_sibis@...cinc.com>
Subject: [PATCH v2 0/2] arm64: dts: qcom: Add missing nodes to X1E80100
base dtsi and CRD dts
This patchset adds most of the nodes towards describing the entire
platform. Most of these have dependencies on multimedia clock
controllers and so the entire patchset depends on the clock controllers
patchset:
https://lore.kernel.org/all/20231214-x1e80100-clock-controllers-v2-0-2b0739bebd27@linaro.org/
Signed-off-by: Abel Vesa <abel.vesa@...aro.org>
---
Changes in v2:
- Reword both commits to make it more clear nodes that are being added
- Dropped comments from interrupt maps from pcie nodes
- Replace all 0x0 with 0 in all reg properties
- Moved on separate lines reg, reset and clock names
- Dropped the sram and cpucp nodes
- Dropped pmic glink node
- Reordered all new clock controller nodes based on address
- Dropped unnecessary indent from touchpad and keyboard TLMM nodes
- Link to v1: https://lore.kernel.org/r/20231212-x1e80100-dts-missing-nodes-v1-0-1472efec2b08@linaro.org
---
Abel Vesa (2):
arm64: dts: qcom: x1e80100: Add all missing nodes
arm64: dts: qcom: x1e80100: Add some issing nodes for CRD
arch/arm64/boot/dts/qcom/x1e80100-crd.dts | 221 +++++
arch/arm64/boot/dts/qcom/x1e80100.dtsi | 1323 ++++++++++++++++++++++++++++-
2 files changed, 1539 insertions(+), 5 deletions(-)
---
base-commit: d0f93829813ccb38ad35811da864672e32595f9c
change-id: 20231201-x1e80100-dts-missing-nodes-a09f1ed99999
Best regards,
--
Abel Vesa <abel.vesa@...aro.org>
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