linux-kernel - [PATCH 01/10] dt-bindings: clock: Add separate clocks for PCIe and USB for Combo PHY

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Message-ID: <20231214062847.2215542-2-quic_ipkumar@quicinc.com>
Date:   Thu, 14 Dec 2023 11:58:38 +0530
From:   Praveenkumar I <quic_ipkumar@...cinc.com>
To:     <agross@...nel.org>, <andersson@...nel.org>,
        <konrad.dybcio@...aro.org>, <mturquette@...libre.com>,
        <sboyd@...nel.org>, <robh+dt@...nel.org>,
        <krzysztof.kozlowski+dt@...aro.org>, <conor+dt@...nel.org>,
        <bhelgaas@...gle.com>, <lpieralisi@...nel.org>, <kw@...ux.com>,
        <vkoul@...nel.org>, <kishon@...nel.org>, <mani@...nel.org>,
        <quic_nsekar@...cinc.com>, <quic_srichara@...cinc.com>,
        <linux-arm-msm@...r.kernel.org>, <linux-clk@...r.kernel.org>,
        <devicetree@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
        <linux-pci@...r.kernel.org>, <linux-phy@...ts.infradead.org>
CC:     <quic_varada@...cinc.com>, <quic_devipriy@...cinc.com>,
        <quic_kathirav@...cinc.com>, <quic_anusha@...cinc.com>
Subject: [PATCH 01/10] dt-bindings: clock: Add separate clocks for PCIe and USB for Combo PHY

Qualcomm IPQ5332 has a combo PHY for PCIe and USB. Either one of the
interface (PCIe/USB) can use this combo PHY and the PHY drivers are
different for PCIe and USB. Hence separate the PCIe and USB pipe clock
source from DT, and individual driver node can be used as a clock source
separately in the gcc. Change the dt-bindings accordingly.

Signed-off-by: Praveenkumar I <quic_ipkumar@...cinc.com>
---
 .../devicetree/bindings/clock/qcom,ipq5332-gcc.yaml         | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/clock/qcom,ipq5332-gcc.yaml b/Documentation/devicetree/bindings/clock/qcom,ipq5332-gcc.yaml
index 718fe0625424..b22643037119 100644
--- a/Documentation/devicetree/bindings/clock/qcom,ipq5332-gcc.yaml
+++ b/Documentation/devicetree/bindings/clock/qcom,ipq5332-gcc.yaml
@@ -28,7 +28,8 @@ properties:
       - description: Sleep clock source
       - description: PCIE 2lane PHY pipe clock source
       - description: PCIE 2lane x1 PHY pipe clock source (For second lane)
-      - description: USB PCIE wrapper pipe clock source
+      - description: PCIE wrapper pipe clock source
+      - description: USB wrapper pipe clock source
 
 required:
   - compatible
@@ -45,7 +46,8 @@ examples:
                <&sleep_clk>,
                <&pcie_2lane_phy_pipe_clk>,
                <&pcie_2lane_phy_pipe_clk_x1>,
-               <&usb_pcie_wrapper_pipe_clk>;
+               <&pcie_wrapper_pipe_clk>,
+               <&usb_wrapper_pipe_clk>;
       #clock-cells = <1>;
       #power-domain-cells = <1>;
       #reset-cells = <1>;
-- 
2.34.1