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Message-ID: <20231215202137.GA317624-robh@kernel.org>
Date: Fri, 15 Dec 2023 14:21:37 -0600
From: Rob Herring <robh@...nel.org>
To: Emil Renner Berthing <emil.renner.berthing@...onical.com>
Cc: linux-gpio@...r.kernel.org, devicetree@...r.kernel.org, linux-kernel@...r.kernel.org, linux-riscv@...ts.infradead.org, Hoan Tran <hoan@...amperecomputing.com>, Serge Semin <fancer.lancer@...il.com>, Linus Walleij <linus.walleij@...aro.org>, Bartosz Golaszewski <brgl@...ev.pl>, Andy Shevchenko <andy@...nel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>, Conor Dooley <conor+dt@...nel.org>, Jisheng Zhang <jszhang@...nel.org>, Guo Ren <guoren@...nel.org>, Fu Wei <wefu@...hat.com>, Paul Walmsley <paul.walmsley@...ive.com>, Palmer Dabbelt <palmer@...belt.com>
Subject: Re: [PATCH v1 1/8] dt-bindings: pinctrl: Add thead,th1520-pinctrl
bindings
On Fri, Dec 15, 2023 at 03:38:59PM +0100, Emil Renner Berthing wrote:
> Add bindings for the pin controllers on the T-Head TH1520 RISC-V SoC.
>
> Signed-off-by: Emil Renner Berthing <emil.renner.berthing@...onical.com>
> ---
> .../pinctrl/thead,th1520-pinctrl.yaml | 156 ++++++++++++++++++
> 1 file changed, 156 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/pinctrl/thead,th1520-pinctrl.yaml
>
> diff --git a/Documentation/devicetree/bindings/pinctrl/thead,th1520-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/thead,th1520-pinctrl.yaml
> new file mode 100644
> index 000000000000..1b1b446cd498
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/pinctrl/thead,th1520-pinctrl.yaml
> @@ -0,0 +1,156 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/pinctrl/thead,th1520-pinctrl.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: T-Head TH1520 SoC pin controller
> +
> +maintainers:
> + - Emil Renner Berthing <emil.renner.berthing@...onical.com>
> +
> +description: |
> + Pinmux and pinconf controller in the T-Head TH1520 RISC-V SoC.
> +
> + The TH1520 has 3 groups of pads each controlled from different memory ranges.
> + Confusingly the memory ranges are named
> + PADCTRL_AOSYS -> PAD Group 1
> + PADCTRL1_APSYS -> PAD Group 2
> + PADCTRL0_APSYS -> PAD Group 3
Are the programming models different?
> +
> + Each pad can be muxed individually to up to 5 different functions. For most
> + pads only a few of those 5 configurations are valid though, and a few pads in
> + group 1 does not support muxing at all.
> +
> + Pinconf is fairly regular except for a few pads in group 1 that either can't
> + be configured or has some special functions. The rest have configurable drive
> + strength, input enable, schmitt trigger, slew rate, pull-up and pull-down in
> + addition to a special strong pull up.
> +
> + Certain pads in group 1 can be muxed to AUDIO_PA0 - AUDIO_PA30 functions and
> + are then meant to be used by the audio co-processor. Each such pad can then
> + be further muxed to either audio GPIO or one of 4 functions such as UART, I2C
> + and I2S. If the audio pad is muxed to one of the 4 functions then pinconf is
> + also configured in different registers. All of this is done from a different
> + AUDIO_IOCTRL memory range and is left to the audio co-processor for now.
> +
> +properties:
> + compatible:
> + enum:
> + - thead,th1520-group1-pinctrl
> + - thead,th1520-group2-pinctrl
> + - thead,th1520-group3-pinctrl
> +
> + reg:
> + maxItems: 1
> +
> +patternProperties:
> + '-[0-9]+$':
Please make this a bit more specific. "-grp-[0-9]+$"?
> + type: object
blank line. And move additionalProperties here. Easier to read in the
indented cases.
> + patternProperties:
> + '-pins$':
> + type: object
> + $ref: /schemas/pinctrl/pincfg-node.yaml
> + description:
> + A pinctrl node should contain at least one subnode describing one
> + or more pads and their associated pinmux and pinconf settings.
> +
> + properties:
> + pins:
> + $ref: /schemas/types.yaml#/definitions/string-array
Type is defined in pinmux-node.yaml. You need to reference it and drop
this.
Normally the possible values are listed out.
> + description: List of pads that properties in the node apply to.
> +
> + function:
> + $ref: /schemas/types.yaml#/definitions/string
> + enum: [ "0", "1", "2", "3", "4", "5" ]
> + description: The mux function to select for the given pins.
> +
> + bias-disable: true
> +
> + bias-pull-up:
> + type: boolean
> +
> + bias-pull-down:
> + type: boolean
> +
> + drive-strength:
> + enum: [ 1, 2, 3, 5, 7, 8, 10, 12, 13, 15, 16, 18, 20, 21, 23, 25 ]
> +
> + input-enable: true
> +
> + input-disable: true
> +
> + input-schmitt-enable: true
> +
> + input-schmitt-disable: true
> +
> + slew-rate:
> + maximum: 1
> +
> + thead,strong-pull-up:
> + oneOf:
> + - type: boolean
> + - $ref: /schemas/types.yaml#/definitions/uint32
> + enum: [ 0, 2100 ]
> + description: Enable or disable strong 2.1kOhm pull-up.
bias-pull-up can already specify the strength in Ohms.
> +
> + required:
> + - pins
> +
> + additionalProperties: false
> +
> + additionalProperties: false
> +
> +required:
> + - compatible
> + - reg
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + padctrl0_apsys: pinctrl@...07000 {
> + compatible = "thead,th1520-group3-pinctrl";
> + reg = <0xec007000 0x1000>;
> +
> + uart0_pins: uart0-0 {
> + tx-pins {
> + pins = "UART0_TXD";
> + function = "0";
> + bias-disable;
> + drive-strength = <3>;
> + input-disable;
> + input-schmitt-disable;
> + slew-rate = <0>;
> + };
> +
> + rx-pins {
> + pins = "UART0_RXD";
> + function = "0";
> + bias-disable;
> + drive-strength = <1>;
> + input-enable;
> + input-schmitt-enable;
> + slew-rate = <0>;
> + };
> + };
> + };
> +
> + padctrl1_apsys: pinctrl@...3c000 {
> + compatible = "thead,th1520-group2-pinctrl";
> + reg = <0xe7f3c000 0x1000>;
> +
> + i2c5_pins: i2c5-0 {
> + i2c-pins {
> + pins = "QSPI1_CSN0", /* I2C5_SCL */
> + "QSPI1_D0_MOSI"; /* I2C5_SDA */
> + function = "2";
> + bias-disable;
> + drive-strength = <7>;
> + input-enable;
> + input-schmitt-enable;
> + slew-rate = <0>;
> + thead,strong-pull-up;
> + };
> + };
> + };
> --
> 2.40.1
>
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