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Message-ID: <20231215081003.8373-1-zhifeng.tang@unisoc.com>
Date: Fri, 15 Dec 2023 16:10:03 +0800
From: Zhifeng Tang <zhifeng.tang@...soc.com>
To: Michael Turquette <mturquette@...libre.com>,
        Stephen Boyd
	<sboyd@...nel.org>, Rob Herring <robh+dt@...nel.org>,
        Krzysztof Kozlowski
	<krzysztof.kozlowski+dt@...aro.org>,
        Conor Dooley <conor+dt@...nel.org>, Orson Zhai <orsonzhai@...il.com>,
        Baolin Wang
	<baolin.wang@...ux.alibaba.com>,
        Chunyan Zhang <zhang.lyra@...il.com>
CC: <linux-clk@...r.kernel.org>, <devicetree@...r.kernel.org>,
        <linux-kernel@...r.kernel.org>,
        Zhifeng Tang <zhifeng.tang23@...il.com>,
        Wenming Wu <wenming.wu@...soc.com>
Subject: [PATCH 4/4] dt-bindings: clock: Add reset controller bindings for Unisoc's UMS512.

Add Reset Controller bindings to clock bindings for Unisoc's UMS512.

Signed-off-by: Zhifeng Tang <zhifeng.tang@...soc.com>
---
 Documentation/devicetree/bindings/clock/sprd,ums512-clk.yaml | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/Documentation/devicetree/bindings/clock/sprd,ums512-clk.yaml b/Documentation/devicetree/bindings/clock/sprd,ums512-clk.yaml
index 43d2b6c31357..6b0892d637fe 100644
--- a/Documentation/devicetree/bindings/clock/sprd,ums512-clk.yaml
+++ b/Documentation/devicetree/bindings/clock/sprd,ums512-clk.yaml
@@ -34,6 +34,9 @@ properties:
   "#clock-cells":
     const: 1
 
+  "#reset-cells":
+    const: 1
+
   clocks:
     minItems: 1
     maxItems: 4
-- 
2.17.1


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