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Message-ID: <fb540d91-0b1e-49e9-a1c9-b87e54ba9ba2@linaro.org>
Date: Fri, 15 Dec 2023 09:35:52 +0100
From: Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>
To: Praveenkumar I <quic_ipkumar@...cinc.com>, agross@...nel.org,
andersson@...nel.org, konrad.dybcio@...aro.org, mturquette@...libre.com,
sboyd@...nel.org, robh+dt@...nel.org, krzysztof.kozlowski+dt@...aro.org,
conor+dt@...nel.org, bhelgaas@...gle.com, lpieralisi@...nel.org,
kw@...ux.com, vkoul@...nel.org, kishon@...nel.org, mani@...nel.org,
quic_nsekar@...cinc.com, quic_srichara@...cinc.com,
linux-arm-msm@...r.kernel.org, linux-clk@...r.kernel.org,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
linux-pci@...r.kernel.org, linux-phy@...ts.infradead.org
Cc: quic_varada@...cinc.com, quic_devipriy@...cinc.com,
quic_kathirav@...cinc.com, quic_anusha@...cinc.com
Subject: Re: [PATCH 07/10] dt-bindings: PCI: qcom: Add IPQ5332 SoC
On 14/12/2023 07:28, Praveenkumar I wrote:
> Add support for the PCIe controller on the Qualcomm
> IPQ5332 SoC to the bindings.
>
> Signed-off-by: Praveenkumar I <quic_ipkumar@...cinc.com>
> ---
> .../devicetree/bindings/pci/qcom,pcie.yaml | 36 +++++++++++++++++++
> 1 file changed, 36 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
> index eadba38171e1..af5e67d2a984 100644
> --- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
> +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
> @@ -21,6 +21,7 @@ properties:
> - qcom,pcie-apq8064
> - qcom,pcie-apq8084
> - qcom,pcie-ipq4019
> + - qcom,pcie-ipq5332
> - qcom,pcie-ipq6018
> - qcom,pcie-ipq8064
> - qcom,pcie-ipq8064-v2
> @@ -170,6 +171,7 @@ allOf:
> compatible:
> contains:
> enum:
> + - qcom,pcie-ipq5332
> - qcom,pcie-ipq6018
> - qcom,pcie-ipq8074-gen3
> then:
> @@ -332,6 +334,39 @@ allOf:
> - const: ahb # AHB reset
> - const: phy_ahb # PHY AHB reset
>
> + - if:
> + properties:
> + compatible:
> + contains:
> + enum:
> + - qcom,pcie-ipq5332
> + then:
> + properties:
> + clocks:
> + minItems: 6
> + maxItems: 6
> + clock-names:
> + items:
> + - const: ahb # AHB clock
> + - const: aux # Auxiliary clock
> + - const: axi_m # AXI Master clock
> + - const: axi_s # AXI Slave clock
> + - const: axi_bridge # AXI bridge clock
> + - const: rchng
> + resets:
> + minItems: 8
> + maxItems: 8
> + reset-names:
> + items:
> + - const: pipe # PIPE reset
No sleep reset? Otherwise it looks like some existing entry, so you
should use the same order of resets.
Best regards,
Krzysztof
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