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Message-ID: <fd927698-6aa3-4a6b-988c-fc82663235ca@linaro.org>
Date: Fri, 15 Dec 2023 11:36:25 +0100
From: Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>
To: Chunyan Zhang <chunyan.zhang@...soc.com>, Rob Herring
<robh+dt@...nel.org>, Krzysztof Kozlowski
<krzysztof.kozlowski+dt@...aro.org>, Conor Dooley <conor+dt@...nel.org>,
Lee Jones <lee@...nel.org>
Cc: devicetree@...r.kernel.org, linux-serial@...r.kernel.org,
Baolin Wang <baolin.wang@...ux.alibaba.com>, Orson Zhai
<orsonzhai@...il.com>, Chunyan Zhang <zhang.lyra@...il.com>,
LKML <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH 4/4] arm64: dts: sprd: Add support for Unisoc's UMS9620
On 15/12/2023 09:56, Chunyan Zhang wrote:
> Add basic support for Unisoc's UMS9620, with this patch,
> the board ums9620-2h10 can run into console.
>
...
> +
> + soc: soc {
Are you sure you do not have here W=1 warnings?
> + compatible = "simple-bus";
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> +
> + gic: interrupt-controller@...00000 {
> + compatible = "arm,gic-v3";
> + reg = <0x0 0x12000000 0 0x20000>, /* GICD */
> + <0x0 0x12040000 0 0x100000>; /* GICR */
> + #interrupt-cells = <3>;
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
Put ranges after reg, if they are needed. Are they needed, BTW?
> + redistributor-stride = <0x0 0x20000>; /* 128KB stride */
> + #redistributor-regions = <1>;
> + interrupt-controller;
> + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
> + };
> +
> + apb@...00000 {
> + compatible = "simple-bus";
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges = <0 0 0x20200000 0x100000>;
ranges is after reg, which is after compatible, so here it is the second
property.
> +
> + uart0: serial@0 {
> + compatible = "sprd,ums9620-uart",
> + "sprd,sc9836-uart";
> + reg = <0 0x100>;
> + interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&ext_26m>;
> + status = "disabled";
> + };
> +
> + uart1: serial@...00 {
> + compatible = "sprd,ums9620-uart",
> + "sprd,sc9836-uart";
> + reg = <0x10000 0x100>;
> + interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&ext_26m>;
> + status = "disabled";
> + };
> + };
> + };
Best regards,
Krzysztof
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