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Message-Id: <20231215104551.233679-7-eugen.hristev@collabora.com>
Date: Fri, 15 Dec 2023 12:45:51 +0200
From: Eugen Hristev <eugen.hristev@...labora.com>
To: linux-mediatek@...ts.infradead.org
Cc: linux-arm-kernel@...ts.infradead.org,
linux-kernel@...r.kernel.org,
devicetree@...r.kernel.org,
angelogioacchino.delregno@...labora.com,
matthias.bgg@...il.com,
linux-media@...r.kernel.org,
tiffany.lin@...iatek.com,
andrew-ct.chen@...iatek.com,
Kyrie Wu <kyrie.wu@...iatek.com>,
Allen-KH Cheng <allen-kh.cheng@...iatek.com>,
Hsin-Yi Wang <hsinyi@...omium.org>,
Eugen Hristev <eugen.hristev@...labora.com>
Subject: [PATCH v2 7/7] arm64: dts: mediatek: mt8186: Add venc node
From: Kyrie Wu <kyrie.wu@...iatek.com>
Add video encoder node.
Signed-off-by: Kyrie Wu <kyrie.wu@...iatek.com>
Signed-off-by: Allen-KH Cheng <allen-kh.cheng@...iatek.com>
Reviewed-by: Hsin-Yi Wang <hsinyi@...omium.org>
[eugen.hristev@...labora.com: minor cleanup]
Signed-off-by: Eugen Hristev <eugen.hristev@...labora.com>
---
Changes in v2:
- change node name
- change compatible to include 8186
- change props order
- change clock name to cope with binding
arch/arm64/boot/dts/mediatek/mt8186.dtsi | 24 ++++++++++++++++++++++++
1 file changed, 24 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8186.dtsi b/arch/arm64/boot/dts/mediatek/mt8186.dtsi
index 66ead3f23336..ebd07bf3d9d2 100644
--- a/arch/arm64/boot/dts/mediatek/mt8186.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8186.dtsi
@@ -1993,6 +1993,30 @@ larb7: smi@...10000 {
power-domains = <&spm MT8186_POWER_DOMAIN_VENC>;
};
+ venc: video-encoder@...20000 {
+ compatible = "mediatek,mt8186-vcodec-enc", "mediatek,mt8183-vcodec-enc";
+ reg = <0 0x17020000 0 0x2000>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH 0>;
+ iommus = <&iommu_mm IOMMU_PORT_L7_VENC_RCPU>,
+ <&iommu_mm IOMMU_PORT_L7_VENC_REC>,
+ <&iommu_mm IOMMU_PORT_L7_VENC_BSDMA>,
+ <&iommu_mm IOMMU_PORT_L7_VENC_SV_COMV>,
+ <&iommu_mm IOMMU_PORT_L7_VENC_RD_COMV>,
+ <&iommu_mm IOMMU_PORT_L7_VENC_CUR_LUMA>,
+ <&iommu_mm IOMMU_PORT_L7_VENC_CUR_CHROMA>,
+ <&iommu_mm IOMMU_PORT_L7_VENC_REF_LUMA>,
+ <&iommu_mm IOMMU_PORT_L7_VENC_REF_CHROMA>;
+ dma-ranges = <0x1 0x0 0x1 0x0 0x1 0x0>;
+ clocks = <&vencsys CLK_VENC_CKE1_VENC>;
+ clock-names = "venc_sel";
+ assigned-clocks = <&topckgen CLK_TOP_VENC>;
+ assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D3>;
+ power-domains = <&spm MT8186_POWER_DOMAIN_VENC>;
+ mediatek,scp = <&scp>;
+ };
+
camsys: clock-controller@...00000 {
compatible = "mediatek,mt8186-camsys";
reg = <0 0x1a000000 0 0x1000>;
--
2.34.1
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