lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC | |
Open Source and information security mailing list archives
| ||
|
Message-ID: <752b98e31a2b9e4cf0aec860f158c53c.sboyd@kernel.org> Date: Sat, 16 Dec 2023 17:21:08 -0800 From: Stephen Boyd <sboyd@...nel.org> To: Jay Buddhabhatti <jay.buddhabhatti@....com>, michal.simek@....com, mturquette@...libre.com, shubhrajyoti.datta@...inx.com Cc: linux-clk@...r.kernel.org, linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org, Jay Buddhabhatti <jay.buddhabhatti@....com> Subject: Re: [PATCH RESEND v2 2/2] drivers: clk: zynqmp: update divider round rate logic Quoting Jay Buddhabhatti (2023-11-29 03:29:16) > Currently zynqmp divider round rate is considering single parent and > calculating rate and parent rate accordingly. But if divider clock flag > is set to SET_RATE_PARENT then its not trying to traverse through all > parent rate and not selecting best parent rate from that. So use common > divider_round_rate() which is traversing through all clock parents and > its rate and calculating proper parent rate. > > Fixes: 3fde0e16d016 ("drivers: clk: Add ZynqMP clock driver") > Signed-off-by: Jay Buddhabhatti <jay.buddhabhatti@....com> > --- Applied to clk-next
Powered by blists - more mailing lists