linux-kernel - Re: [PATCH v8 14/14] dt-bindings: net: ar803x: add qca8084 PHY properties

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Date: Mon, 18 Dec 2023 12:53:04 +0800
From: Jie Luo <quic_luoj@...cinc.com>
To: Andrew Lunn <andrew@...n.ch>
CC: "Russell King (Oracle)" <linux@...linux.org.uk>,
        Krzysztof Kozlowski
	<krzysztof.kozlowski@...aro.org>,
        <davem@...emloft.net>, <edumazet@...gle.com>, <kuba@...nel.org>,
        <pabeni@...hat.com>, <robh+dt@...nel.org>,
        <krzysztof.kozlowski+dt@...aro.org>, <conor+dt@...nel.org>,
        <hkallweit1@...il.com>, <corbet@....net>, <p.zabel@...gutronix.de>,
        <f.fainelli@...il.com>, <netdev@...r.kernel.org>,
        <devicetree@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
        <linux-doc@...r.kernel.org>
Subject: Re: [PATCH v8 14/14] dt-bindings: net: ar803x: add qca8084 PHY
 properties



On 12/17/2023 1:17 AM, Andrew Lunn wrote:
>> Yes, Russell, i will add an example in the DT doc in the next patch set.
>> The following is the device node used for the current qca8084 PHY
>> code design.
> 
> If you look at Christians work, this would be expressed differently:
> 
>> mdio: mdio@...00 {
>>      ethernet-phy-package@1 {
>>
>>          compatible = "qca,qca8084-package";
>>
>>          qcom,phy-work-mode = <2>;
>>          clocks = <&qca8k_nsscc NSS_CC_APB_BRIDGE_CLK>,
>>                 <&qca8k_nsscc NSS_CC_AHB_CLK>,
>>                 <&qca8k_nsscc NSS_CC_SEC_CTRL_AHB_CLK>,
>>                 <&qca8k_nsscc NSS_CC_TLMM_CLK>,
>>                 <&qca8k_nsscc NSS_CC_TLMM_AHB_CLK>,
>>                 <&qca8k_nsscc NSS_CC_CNOC_AHB_CLK>,
>>                 <&qca8k_nsscc NSS_CC_MDIO_AHB_CLK>,
>>                 <&qca8k_nsscc NSS_CC_MDIO_MASTER_AHB_CLK>,
>>                 <&qca8k_nsscc NSS_CC_SRDS0_SYS_CLK>,
>>                 <&qca8k_nsscc NSS_CC_SRDS1_SYS_CLK>;
>>          clock-names = "apb_bridge",
>>                  "ahb",
>>                  "sec_ctrl_ahb",
>>                  "tlmm",
>>                  "tlmm_ahb",
>>                  "cnoc_ahb",
>>                  "mdio_ahb",
>>                  "mdio_master_ahb",
>>                  "srds0_sys",
>>                  "srds1_sys";
>>          resets = <&qca8k_nsscc NSS_CC_SRDS0_SYS_ARES>,
>>                 <&qca8k_nsscc NSS_CC_SRDS1_SYS_ARES>,
>>                 <&qca8k_nsscc NSS_CC_DSP_ARES>;
>>          reset-names = "srds0_sys",
>>                        "srds1_sys";
>>
> 
> All the properties above are common to the package as a whole.
> 
> Then follow the four individual PHYs, and the properties which are
> specific to each one.

Thanks Andrew for the proposal.
For the pure PHY chip qca8084, there is no driver to parse the package
level device tree node for common clocks and resets.

For the common clocks and resets above, whether we can add a qca8084
common device tree node as the child node of MDIO bus node, and then
parse these common properties in the PHY probe function? since the DSA
driver is not enabled for the pure PHY chip.

> 
>>
>>          ethernet-phy@0 {
>>              compatible = "ethernet-phy-id004d.d180";
>>              reg = <0>;
>>              clocks = <qca8k_nsscc NSS_CC_GEPHY0_SYS_CLK>,
>>              clock-names = <"gephy_sys">;
>>              resets = <&qca8k_nsscc NSS_CC_GEPHY0_SYS_ARES>,
>>                       <&qca8k_nsscc NSS_CC_GEPHY0_ARES>;
>>              reset-names = "gephy_sys", "gephy_soft";
>>          };
>>      
>>      
>>          ethernet-phy@1 {
>>              compatible = "ethernet-phy-id004d.d180";
>>              reg = <1>;
>>              clocks = <qca8k_nsscc NSS_CC_GEPHY1_SYS_CLK>,
>>              clock-names = <"gephy_sys">;
>>              resets = <&qca8k_nsscc NSS_CC_GEPHY1_SYS_ARES>,
>>                       <&qca8k_nsscc NSS_CC_GEPHY1_ARES>;
>>              reset-names = "gephy_sys", "gephy_soft";
>>      
>>          };
>>      
>>          ethernet-phy@2 {
>>              compatible = "ethernet-phy-id004d.d180";
>>              reg = <2>;
>>              clocks = <qca8k_nsscc NSS_CC_GEPHY2_SYS_CLK>,
>>              clock-names = <"gephy_sys">;
>>              resets = <&qca8k_nsscc NSS_CC_GEPHY2_SYS_ARES>,
>>                       <&qca8k_nsscc NSS_CC_GEPHY2_ARES>;
>>              reset-names = "gephy_sys", "gephy_soft";
>>      
>>          };
>>      
>>          ethernet-phy@3 {
>>              compatible = "ethernet-phy-id004d.d180";
>>              reg = <3>;
>>              clocks = <qca8k_nsscc NSS_CC_GEPHY3_SYS_CLK>,
>>              clock-names = <"gephy_sys">;
>>              reset-names = "gephy_sys", "gephy_soft";
>>          };
>> };
> 
> 	Andrew