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Message-ID: <92471e65e1879f22caaaaa9c706c491b.sboyd@kernel.org>
Date: Sun, 17 Dec 2023 22:32:30 -0800
From: Stephen Boyd <sboyd@...nel.org>
To: Alvin Šipraga <alsi@...g-olufsen.dk>, Alvin Šipraga <alvin@...s.dk>, Conor Dooley <conor+dt@...nel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>, Michael Turquette <mturquette@...libre.com>, Rob Herring <robh+dt@...nel.org>
Cc: Sebastian Hesselbarth <sebastian.hesselbarth@...il.com>, Rabeeh Khoury <rabeeh@...id-run.com>, Jacob Siverskog <jacob@...nage.engineering>, Sergej Sawazki <sergej@...dac.com>, linux-clk@...r.kernel.org, devicetree@...r.kernel.org, linux-kernel@...r.kernel.org, Rob Herring <robh@...nel.org>
Subject: Re: [PATCH v6 2/3] dt-bindings: clock: si5351: add PLL reset mode property
Quoting Alvin Šipraga (2023-11-24 05:17:43)
> From: Alvin Šipraga <alsi@...g-olufsen.dk>
>
> For applications where the PLL must be adjusted without glitches in the
> clock output(s), a new silabs,pll-reset-mode property is added. It
> can be used to specify whether or not the PLL should be reset after
> adjustment. Resetting is known to cause glitches.
>
> For compatibility with older device trees, it must be assumed that the
> default PLL reset mode is to unconditionally reset after adjustment.
>
> Cc: Sebastian Hesselbarth <sebastian.hesselbarth@...il.com>
> Cc: Rabeeh Khoury <rabeeh@...id-run.com>
> Cc: Jacob Siverskog <jacob@...nage.engineering>
> Cc: Sergej Sawazki <sergej@...dac.com>
> Reviewed-by: Rob Herring <robh@...nel.org>
> Signed-off-by: Alvin Šipraga <alsi@...g-olufsen.dk>
> ---
Applied to clk-next
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