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Message-ID: <20231218030430.783495-4-LeoLiu-oc@zhaoxin.com>
Date: Mon, 18 Dec 2023 11:04:30 +0800
From: LeoLiu-oc <LeoLiu-oc@...oxin.com>
To: <rafael@...nel.org>, <lenb@...nel.org>, <james.morse@....com>,
<tony.luck@...el.com>, <bp@...en8.de>, <bhelgaas@...gle.com>,
<robert.moore@...el.com>, <linux-acpi@...r.kernel.org>,
<linux-kernel@...r.kernel.org>, <linux-pci@...r.kernel.org>,
<acpica-devel@...ts.linux.dev>
CC: <CobeChen@...oxin.com>, <TonyWWang@...oxin.com>, <ErosZhang@...oxin.com>,
<LeoLiu@...oxin.com>, LeoLiuoc <LeoLiu-oc@...oxin.com>
Subject: [PATCH v2 3/3] PCI/ACPI: Add pci_acpi_program_hest_aer_params()
From: LeoLiuoc <LeoLiu-oc@...oxin.com>
Call the func pci_acpi_program_hest_aer_params() for every PCIe device,
the purpose of this function is to extract register value from HEST PCIe
AER structures and program them into AER Capabilities.
Signed-off-by: LeoLiuoc <LeoLiu-oc@...oxin.com>
---
drivers/pci/pci-acpi.c | 98 ++++++++++++++++++++++++++++++++++++++++++
drivers/pci/pci.h | 9 ++++
drivers/pci/probe.c | 1 +
3 files changed, 108 insertions(+)
diff --git a/drivers/pci/pci-acpi.c b/drivers/pci/pci-acpi.c
index 004575091596..3a183d5e20cb 100644
--- a/drivers/pci/pci-acpi.c
+++ b/drivers/pci/pci-acpi.c
@@ -18,6 +18,7 @@
#include <linux/pm_runtime.h>
#include <linux/pm_qos.h>
#include <linux/rwsem.h>
+#include <acpi/apei.h>
#include "pci.h"
/*
@@ -783,6 +784,103 @@ int pci_acpi_program_hp_params(struct pci_dev *dev)
return -ENODEV;
}
+#ifdef CONFIG_ACPI_APEI
+static void program_hest_aer_endpoint(struct acpi_hest_aer_common aer_endpoint,
+ struct pci_dev *dev, int pos)
+{
+ u32 uncor_mask;
+ u32 uncor_severity;
+ u32 cor_mask;
+ u32 adv_cap;
+
+ uncor_mask = aer_endpoint.uncorrectable_mask;
+ uncor_severity = aer_endpoint.uncorrectable_severity;
+ cor_mask = aer_endpoint.correctable_mask;
+ adv_cap = aer_endpoint.advanced_capabilities;
+
+ pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_MASK, uncor_mask);
+ pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_SEVER, uncor_severity);
+ pci_write_config_dword(dev, pos + PCI_ERR_COR_MASK, cor_mask);
+ pci_write_config_dword(dev, pos + PCI_ERR_CAP, adv_cap);
+}
+
+static void program_hest_aer_root(struct acpi_hest_aer_root *aer_root, struct pci_dev *dev, int pos)
+{
+ u32 root_err_cmd;
+
+ root_err_cmd = aer_root->root_error_command;
+
+ pci_write_config_dword(dev, pos + PCI_ERR_ROOT_COMMAND, root_err_cmd);
+}
+
+static void program_hest_aer_bridge(struct acpi_hest_aer_bridge *hest_aer_bridge,
+ struct pci_dev *dev, int pos)
+{
+ u32 uncor_mask2;
+ u32 uncor_severity2;
+ u32 adv_cap2;
+
+ uncor_mask2 = hest_aer_bridge->uncorrectable_mask2;
+ uncor_severity2 = hest_aer_bridge->uncorrectable_severity2;
+ adv_cap2 = hest_aer_bridge->advanced_capabilities2;
+
+ pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_MASK2, uncor_mask2);
+ pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_SEVER2, uncor_severity2);
+ pci_write_config_dword(dev, pos + PCI_ERR_CAP2, adv_cap2);
+}
+
+static void program_hest_aer_params(struct hest_parse_aer_info info)
+{
+ struct pci_dev *dev;
+ int port_type;
+ int pos;
+ struct acpi_hest_aer_root *hest_aer_root;
+ struct acpi_hest_aer *hest_aer_endpoint;
+ struct acpi_hest_aer_bridge *hest_aer_bridge;
+
+ dev = info.pci_dev;
+ port_type = pci_pcie_type(dev);
+ pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR);
+ if (!pos)
+ return;
+
+ switch (port_type) {
+ case PCI_EXP_TYPE_ROOT_PORT:
+ hest_aer_root = info.hest_aer_root_port;
+ program_hest_aer_endpoint(hest_aer_root->aer, dev, pos);
+ program_hest_aer_root(hest_aer_root, dev, pos);
+ break;
+ case PCI_EXP_TYPE_ENDPOINT:
+ hest_aer_endpoint = info.hest_aer_endpoint;
+ program_hest_aer_endpoint(hest_aer_endpoint->aer, dev, pos);
+ break;
+ case PCI_EXP_TYPE_PCI_BRIDGE:
+ case PCI_EXP_TYPE_PCIE_BRIDGE:
+ hest_aer_bridge = info.hest_aer_bridge;
+ program_hest_aer_endpoint(hest_aer_bridge->aer, dev, pos);
+ program_hest_aer_bridge(hest_aer_bridge, dev, pos);
+ break;
+ default:
+ return;
+ }
+}
+
+int pci_acpi_program_hest_aer_params(struct pci_dev *dev)
+{
+ struct hest_parse_aer_info info = {
+ .pci_dev = dev
+ };
+
+ if (!pci_is_pcie(dev))
+ return -ENODEV;
+
+ if (apei_hest_parse(hest_parse_pcie_aer, &info) == 1)
+ program_hest_aer_params(info);
+
+ return 0;
+}
+#endif
+
/**
* pciehp_is_native - Check whether a hotplug port is handled by the OS
* @bridge: Hotplug port to check
diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h
index 5ecbcf041179..1fc28f7a5972 100644
--- a/drivers/pci/pci.h
+++ b/drivers/pci/pci.h
@@ -714,6 +714,15 @@ static inline void pci_save_aer_state(struct pci_dev *dev) { }
static inline void pci_restore_aer_state(struct pci_dev *dev) { }
#endif
+#ifdef CONFIG_ACPI_APEI
+int pci_acpi_program_hest_aer_params(struct pci_dev *dev);
+#else
+static inline int pci_acpi_program_hest_aer_params(struct pci_dev *dev)
+{
+ return 0;
+}
+#endif
+
#ifdef CONFIG_ACPI
int pci_acpi_program_hp_params(struct pci_dev *dev);
extern const struct attribute_group pci_dev_acpi_attr_group;
diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c
index ed6b7f48736a..45a45ab72846 100644
--- a/drivers/pci/probe.c
+++ b/drivers/pci/probe.c
@@ -2274,6 +2274,7 @@ static void pci_configure_device(struct pci_dev *dev)
pci_configure_serr(dev);
pci_acpi_program_hp_params(dev);
+ pci_acpi_program_hest_aer_params(dev);
}
static void pci_release_capabilities(struct pci_dev *dev)
--
2.34.1
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