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Message-ID:
<IA1PR20MB49535284E78A301FCFBB5882BB90A@IA1PR20MB4953.namprd20.prod.outlook.com>
Date: Mon, 18 Dec 2023 12:06:28 +0800
From: Inochi Amaoto <inochiama@...look.com>
To: Rob Herring <robh+dt@...nel.org>
Cc: Inochi Amaoto <inochiama@...look.com>,
Michael Turquette <mturquette@...libre.com>,
Stephen Boyd <sboyd@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Conor Dooley <conor+dt@...nel.org>,
Chao Wei <chao.wei@...hgo.com>,
Chen Wang <unicorn_wang@...look.com>,
Paul Walmsley <paul.walmsley@...ive.com>,
Palmer Dabbelt <palmer@...belt.com>,
Albert Ou <aou@...s.berkeley.edu>,
Jisheng Zhang <jszhang@...nel.org>,
Liu Gui <kenneth.liu@...hgo.com>,
Emil Renner Berthing <emil.renner.berthing@...onical.com>,
qiujingbao.dlmu@...il.com,
dlan@...too.org,
linux-clk@...r.kernel.org,
devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org,
linux-riscv@...ts.infradead.org
Subject: Re: [PATCH v3 2/4] clk: sophgo: Add CV1800 series clock controller driver
>On Thu, Dec 7, 2023 at 2:37 AM Inochi Amaoto <inochiama@...look.com> wrote:
>>
>> Add driver for CV1800 series clock controller.
>>
>> Signed-off-by: Inochi Amaoto <inochiama@...look.com>
>> Link: https://github.com/milkv-duo/duo-files/blob/main/hardware/CV1800B/CV180X-Clock-v1.xlsx
>> Link: https://github.com/milkv-duo/duo-files/blob/main/hardware/CV1800B/CV1800B-CV1801B-Preliminary-Datasheet-full-en.pdf
>> ---
>> drivers/clk/Kconfig | 1 +
>> drivers/clk/Makefile | 1 +
>> drivers/clk/sophgo/Kconfig | 12 +
>> drivers/clk/sophgo/Makefile | 7 +
>> drivers/clk/sophgo/clk-cv1800.c | 1574 ++++++++++++++++++++++++
>> drivers/clk/sophgo/clk-cv1800.h | 123 ++
>> drivers/clk/sophgo/clk-cv18xx-common.c | 76 ++
>> drivers/clk/sophgo/clk-cv18xx-common.h | 85 ++
>> drivers/clk/sophgo/clk-cv18xx-ip.c | 894 ++++++++++++++
>> drivers/clk/sophgo/clk-cv18xx-ip.h | 266 ++++
>> drivers/clk/sophgo/clk-cv18xx-pll.c | 465 +++++++
>> drivers/clk/sophgo/clk-cv18xx-pll.h | 79 ++
>> 12 files changed, 3583 insertions(+)
>> create mode 100644 drivers/clk/sophgo/Kconfig
>> create mode 100644 drivers/clk/sophgo/Makefile
>> create mode 100644 drivers/clk/sophgo/clk-cv1800.c
>> create mode 100644 drivers/clk/sophgo/clk-cv1800.h
>> create mode 100644 drivers/clk/sophgo/clk-cv18xx-common.c
>> create mode 100644 drivers/clk/sophgo/clk-cv18xx-common.h
>> create mode 100644 drivers/clk/sophgo/clk-cv18xx-ip.c
>> create mode 100644 drivers/clk/sophgo/clk-cv18xx-ip.h
>> create mode 100644 drivers/clk/sophgo/clk-cv18xx-pll.c
>> create mode 100644 drivers/clk/sophgo/clk-cv18xx-pll.h
>>
>> diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
>> index c30d0d396f7a..514343934fda 100644
>> --- a/drivers/clk/Kconfig
>> +++ b/drivers/clk/Kconfig
>> @@ -499,6 +499,7 @@ source "drivers/clk/rockchip/Kconfig"
>> source "drivers/clk/samsung/Kconfig"
>> source "drivers/clk/sifive/Kconfig"
>> source "drivers/clk/socfpga/Kconfig"
>> +source "drivers/clk/sophgo/Kconfig"
>> source "drivers/clk/sprd/Kconfig"
>> source "drivers/clk/starfive/Kconfig"
>> source "drivers/clk/sunxi/Kconfig"
>> diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
>> index ed71f2e0ee36..eeae7ae93f89 100644
>> --- a/drivers/clk/Makefile
>> +++ b/drivers/clk/Makefile
>> @@ -119,6 +119,7 @@ obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/
>> obj-$(CONFIG_COMMON_CLK_SAMSUNG) += samsung/
>> obj-$(CONFIG_CLK_SIFIVE) += sifive/
>> obj-y += socfpga/
>> +obj-y += sophgo/
>> obj-$(CONFIG_PLAT_SPEAR) += spear/
>> obj-y += sprd/
>> obj-$(CONFIG_ARCH_STI) += st/
>> diff --git a/drivers/clk/sophgo/Kconfig b/drivers/clk/sophgo/Kconfig
>> new file mode 100644
>> index 000000000000..d67009fa749f
>> --- /dev/null
>> +++ b/drivers/clk/sophgo/Kconfig
>> @@ -0,0 +1,12 @@
>> +# SPDX-License-Identifier: GPL-2.0
>> +# common clock support for SOPHGO SoC family.
>> +
>> +config CLK_SOPHGO_CV1800
>> + tristate "Support for the Sophgo CV1800 series SoCs clock controller"
>> + default m
>> + depends on ARCH_SOPHGO || COMPILE_TEST
>> + help
>> + This driver supports clock controller of Sophgo CV18XX series SoC.
>> + The driver require a 25MHz Oscillator to function generate clock.
>> + It includes PLLs, common clock function and some vendor clock for
>> + IPs of CV18XX series SoC
>> diff --git a/drivers/clk/sophgo/Makefile b/drivers/clk/sophgo/Makefile
>> new file mode 100644
>> index 000000000000..a50320764200
>> --- /dev/null
>> +++ b/drivers/clk/sophgo/Makefile
>> @@ -0,0 +1,7 @@
>> +# SPDX-License-Identifier: GPL-2.0
>> +obj-$(CONFIG_CLK_SOPHGO_CV1800) += clk-sophgo-cv1800.o
>> +
>> +clk-sophgo-cv1800-y += clk-cv1800.o
>> +clk-sophgo-cv1800-y += clk-cv18xx-common.o
>> +clk-sophgo-cv1800-y += clk-cv18xx-ip.o
>> +clk-sophgo-cv1800-y += clk-cv18xx-pll.o
>> diff --git a/drivers/clk/sophgo/clk-cv1800.c b/drivers/clk/sophgo/clk-cv1800.c
>> new file mode 100644
>> index 000000000000..8176ee672190
>> --- /dev/null
>> +++ b/drivers/clk/sophgo/clk-cv1800.c
>> @@ -0,0 +1,1574 @@
>> +// SPDX-License-Identifier: GPL-2.0
>> +/*
>> + * Copyright (C) 2023 Inochi Amaoto <inochiama@...look.com>
>> + */
>> +
>> +#include <linux/clk-provider.h>
>> +#include <linux/clk.h>
>> +#include <linux/clkdev.h>
>> +#include <linux/kernel.h>
>> +#include <linux/module.h>
>
>> +#include <linux/of_address.h>
>> +#include <linux/of_device.h>
>
>You probably don't need these 2 headers and the implicit includes it
>makes are dropped now in linux-next. Please check what you actually
>need and make them explicit.
>
>Rob
>
Thanks. I have fixed in the new version.
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