linux-kernel - Re: [PATCH v5 2/2] mmc: add new sdhci reset sequence for brcm 74165b0

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <45b785bd-9b60-4ab7-80f9-b179d932d04d@broadcom.com>
Date: Tue, 19 Dec 2023 22:55:38 +0100
From: Florian Fainelli <florian.fainelli@...adcom.com>
To: Kamal Dasu <kamal.dasu@...adcom.com>, ulf.hansson@...aro.org,
 linux-kernel@...r.kernel.org, alcooperx@...il.com,
 linux-arm-kernel@...ts.infradead.org, adrian.hunter@...el.com,
 linux-mmc@...r.kernel.org, robh+dt@...nel.org,
 krzysztof.kozlowski+dt@...aro.org, conor+dt@...nel.org,
 devicetree@...r.kernel.org
Cc: f.fainelli@...il.com, bcm-kernel-feedback-list@...adcom.com,
 Kamal Dasu <kdasu@...adcom.com>
Subject: Re: [PATCH v5 2/2] mmc: add new sdhci reset sequence for brcm 74165b0

Hi Kamal,

On 12/19/2023 5:22 PM, Kamal Dasu wrote:
> From: Kamal Dasu <kdasu@...adcom.com>
> 
> 74165b0 shall use a new sdio controller core version which
> requires a different reset sequence. For core reset we use
> sdhci_reset. For CMD and/or DATA reset added a new function
> to also enable SDHCI clocks SDHCI_CLOCK_CARD_EN
> SDHCI_CLOCK_INT_EN along with the SDHCI_RESET_CMD and/or
> SDHCI_RESET_DATA fields.
> 
> Signed-off-by: Kamal Dasu <kdasu@...adcom.com>
> ---

[snip]

> +static void brcmstb_sdhci_reset_cmd_data(struct sdhci_host *host, u8 mask)
> +{
> +	int ret;
> +	u32 reg;
> +	u32 new_mask = (mask &  (SDHCI_RESET_CMD | SDHCI_RESET_DATA)) << 24;
> +
> +	/*
> +	 * SDHCI_CLOCK_CONTROL register CARD_EN and CLOCK_INT_EN bits shall
> +	 * be set along with SOFTWARE_RESET register RESET_CMD or RESET_DATA
> +	 * bits, hence access SDHCI_CLOCK_CONTROL register as 32-bit register
> +	 */
> +	new_mask |= SDHCI_CLOCK_CARD_EN | SDHCI_CLOCK_INT_EN;
> +	reg = sdhci_readl(host, SDHCI_CLOCK_CONTROL);
> +	sdhci_writel(host, reg | new_mask, SDHCI_CLOCK_CONTROL);
> +
> +	reg = sdhci_readb(host, SDHCI_SOFTWARE_RESET);
> +	ret = readb_poll_timeout(host->ioaddr + SDHCI_SOFTWARE_RESET,
> +				 reg, reg & mask, 10, 10000);

Does this need to be readb_poll_timeout_atomic() since this function can 
be used in both atomic and non-atomic context AFAIR?
-- 
Florian

Download attachment "smime.p7s" of type "application/pkcs7-signature" (4221 bytes)