linux-kernel - [PATCH v7 14/16] x86/sev: Mark Secure TSC as reliable

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Message-ID: <20231220151358.2147066-15-nikunj@amd.com>
Date: Wed, 20 Dec 2023 20:43:56 +0530
From: Nikunj A Dadhania <nikunj@....com>
To: <linux-kernel@...r.kernel.org>, <thomas.lendacky@....com>,
	<x86@...nel.org>, <kvm@...r.kernel.org>
CC: <bp@...en8.de>, <mingo@...hat.com>, <tglx@...utronix.de>,
	<dave.hansen@...ux.intel.com>, <dionnaglaze@...gle.com>, <pgonda@...gle.com>,
	<seanjc@...gle.com>, <pbonzini@...hat.com>, <nikunj@....com>
Subject: [PATCH v7 14/16] x86/sev: Mark Secure TSC as reliable

AMD SNP guests may have Secure TSC feature enabled. Use the Secure TSC
as the only reliable clock source in SEV-SNP guests when enabled,
bypassing unstable calibration.

Signed-off-by: Nikunj A Dadhania <nikunj@....com>
Tested-by: Peter Gonda <pgonda@...gle.com>
---
 arch/x86/mm/mem_encrypt_amd.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/arch/x86/mm/mem_encrypt_amd.c b/arch/x86/mm/mem_encrypt_amd.c
index c81b57ca03b6..cc936999efc8 100644
--- a/arch/x86/mm/mem_encrypt_amd.c
+++ b/arch/x86/mm/mem_encrypt_amd.c
@@ -498,6 +498,10 @@ void __init sme_early_init(void)
 	 */
 	if (sev_status & MSR_AMD64_SEV_ENABLED)
 		ia32_disable();
+
+	/* Mark the TSC as reliable when Secure TSC is enabled */
+	if (sev_status & MSR_AMD64_SNP_SECURE_TSC)
+		setup_force_cpu_cap(X86_FEATURE_TSC_RELIABLE);
 }
 
 void __init mem_encrypt_free_decrypted_mem(void)
-- 
2.34.1