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Message-ID: <ZYNU36BoLwMVyHPv@lizhi-Precision-Tower-5810>
Date: Wed, 20 Dec 2023 15:55:59 -0500
From: Frank Li <Frank.li@....com>
To: Joshua Yeong <joshua.yeong@...rfivetech.com>
Cc: miquel.raynal@...tlin.com, alexandre.belloni@...tlin.com,
	conor.culhane@...vaco.com, imx@...ts.linux.dev, joe@...ches.com,
	linux-i3c@...ts.infradead.org, linux-kernel@...r.kernel.org,
	zbigniew.lukwinski@...ux.intel.com
Subject: Re: [v5 resend 3/6] i3c: add actual_len in i3c_priv_xfer

On Wed, Dec 20, 2023 at 09:55:26AM +0800, Joshua Yeong wrote:
> 
> On 02/12/2023 6:25 AM, Frank Li wrote:
> > In MIPI I3C Specification:
> > 
> > "Ninth Bit of SDR Target Returned (Read) Data as End-of-Data: In I2C, the
> > ninth Data bit from Target to Controller is an ACK by the Controller. By
> > contrast, in I3C this bit allows the Target to end a Read, and allows the
> > Controller to Abort a Read. In SDR terms, the ninth bit of Read data is
> > referred to as the T-Bit (for ‘Transition’)"
> > 
> > I3C allow devices early terminate data transfer. So need "actual_len" field
> > to indicate how much get by i3c_priv_xfer.
> > 
> > Reviewed-by: Miquel Raynal <miquel.raynal@...tlin.com>
> > Signed-off-by: Frank Li <Frank.Li@....com>
> > ---
> > 
> > Notes:
> >      change from v4 to v5
> >      - Add Miquel review tag
> > 
> >   include/linux/i3c/device.h | 2 ++
> >   1 file changed, 2 insertions(+)
> > 
> > diff --git a/include/linux/i3c/device.h b/include/linux/i3c/device.h
> > index 90fa83464f003..ef6217da8253b 100644
> > --- a/include/linux/i3c/device.h
> > +++ b/include/linux/i3c/device.h
> > @@ -54,6 +54,7 @@ enum i3c_hdr_mode {
> >    * struct i3c_priv_xfer - I3C SDR private transfer
> >    * @rnw: encodes the transfer direction. true for a read, false for a write
> >    * @len: transfer length in bytes of the transfer
> > + * @actual_len: actual length in bytes are transferred by the controller
> >    * @data: input/output buffer
> >    * @data.in: input buffer. Must point to a DMA-able buffer
> >    * @data.out: output buffer. Must point to a DMA-able buffer
> > @@ -62,6 +63,7 @@ enum i3c_hdr_mode {
> >   struct i3c_priv_xfer {
> >   	u8 rnw;
> >   	u16 len;
> What happens if I3C device does not terminate the T-Bit because it expects
> extra length from master?

If devices don't terminate T, there are two cases.

1. Master send STOP, then START new transfer. I3C Devices can decide start
new transfer, or continue transfer left data, which is totally up to how
I3C device and devices' driver implementation.

2. Master continue toggle SCL to get extra data. Just like a low frequency
at short period.

Frank

> > +	u16 actual_len;
> >   	union {
> >   		void *in;
> >   		const void *out;

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