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Message-ID: <c98539f99030f174583d7ee36802b4b9.sboyd@kernel.org>
Date: Wed, 20 Dec 2023 14:16:46 -0800
From: Stephen Boyd <sboyd@...nel.org>
To: Alexandre Torgue <alexandre.torgue@...s.st.com>, Conor Dooley <conor+dt@...nel.org>, Gabriel Fernandez <gabriel.fernandez@...s.st.com>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>, Maxime Coquelin <mcoquelin.stm32@...il.com>, Michael Turquette <mturquette@...libre.com>, Philipp Zabel <p.zabel@...gutronix.de>, Rob Herring <robh+dt@...nel.org>
Cc: linux-clk@...r.kernel.org, devicetree@...r.kernel.org, linux-stm32@...md-mailman.stormreply.com, linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH v7 1/2] clk: stm32: introduce clocks for STM32MP257 platform
Quoting gabriel.fernandez@...s.st.com (2023-12-19 05:09:08)
> diff --git a/drivers/clk/stm32/clk-stm32mp25.c b/drivers/clk/stm32/clk-stm32mp25.c
> new file mode 100644
> index 000000000000..313e022c6142
> --- /dev/null
> +++ b/drivers/clk/stm32/clk-stm32mp25.c
> @@ -0,0 +1,1826 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * Copyright (C) STMicroelectronics 2023 - All Rights Reserved
> + * Author: Gabriel Fernandez <gabriel.fernandez@...s.st.com> for STMicroelectronics.
> + */
> +
> +#include <linux/clk.h>
> +#include <linux/of_address.h>
> +#include <linux/platform_device.h>
> +
> +#include "clk-stm32-core.h"
> +#include "reset-stm32.h"
> +#include "stm32mp25_rcc.h"
> +
> +#include <dt-bindings/clock/st,stm32mp25-rcc.h>
> +#include <dt-bindings/reset/st,stm32mp25-rcc.h>
> +
> +static const struct clk_parent_data adc12_src[] = {
> + { .name = "ck_flexgen_46" },
This is a new driver. Don't use .name here. Instead use .index or .hw
and if that can't work then use .fw_name.
> + { .name = "ck_icn_ls_mcu" },
> +};
> +
> +static const struct clk_parent_data adc3_src[] = {
> + { .name = "ck_flexgen_47" },
> + { .name = "ck_icn_ls_mcu" },
> + { .name = "ck_flexgen_46" },
> +};
[...]
> +static struct clk_stm32_composite ck_ker_usb3pciephy = {
> + .gate_id = GATE_USB3PCIEPHY,
> + .mux_id = MUX_USB3PCIEPHY,
> + .div_id = NO_STM32_DIV,
> + .hw.init = CLK_HW_INIT_PARENTS_DATA("ck_ker_usb3pciephy", usb3pciphy_src,
> + &clk_stm32_composite_ops, 0),
> +};
> +
> +/* USB3 DRD */
> +static struct clk_stm32_gate ck_icn_m_usb3dr = {
> + .gate_id = GATE_USB3DR,
> + .hw.init = CLK_HW_INIT("ck_icn_m_usb3dr", "ck_icn_hsl", &clk_stm32_gate_ops, 0),
> +};
> +
> +static struct clk_stm32_gate ck_ker_usb2phy2 = {
> + .gate_id = GATE_USB3DR,
> + .hw.init = CLK_HW_INIT("ck_ker_usb2phy2", "ck_flexgen_58", &clk_stm32_gate_ops, 0),
> +};
> +
> +/* USBTC */
> +static struct clk_stm32_gate ck_icn_p_usbtc = {
> + .gate_id = GATE_USBTC,
> + .hw.init = CLK_HW_INIT("ck_icn_p_usbtc", "ck_icn_apb4", &clk_stm32_gate_ops, 0),
Please stop using strings to match parents, i.e. don't use CLK_HW_INIT.
> +};
> +
> +static struct clk_stm32_gate ck_ker_usbtc = {
> + .gate_id = GATE_USBTC,
> + .hw.init = CLK_HW_INIT("ck_ker_usbtc", "ck_flexgen_35", &clk_stm32_gate_ops, 0),
> +};
> +
> +/* VDEC / VENC */
> +static struct clk_stm32_gate ck_icn_p_vdec = {
> + .gate_id = GATE_VDEC,
> + .hw.init = CLK_HW_INIT("ck_icn_p_vdec", "ck_icn_apb4", &clk_stm32_gate_ops, 0),
> +};
> +
> +static struct clk_stm32_gate ck_icn_p_venc = {
> + .gate_id = GATE_VENC,
> + .hw.init = CLK_HW_INIT("ck_icn_p_venc", "ck_icn_apb4", &clk_stm32_gate_ops, 0),
> +};
> +
> +/* VREF */
> +static struct clk_stm32_gate ck_icn_p_vref = {
> + .gate_id = GATE_VREF,
> + .hw.init = CLK_HW_INIT("ck_icn_p_vref", "ck_icn_apb3", &clk_stm32_gate_ops, 0),
> +};
> +
> +/* WWDG */
> +static struct clk_stm32_gate ck_icn_p_wwdg1 = {
> + .gate_id = GATE_WWDG1,
> + .hw.init = CLK_HW_INIT("ck_icn_p_wwdg1", "ck_icn_apb3", &clk_stm32_gate_ops, 0),
> +};
> +
> +static struct clk_stm32_gate ck_icn_p_wwdg2 = {
> + .gate_id = GATE_WWDG2,
> + .hw.init = CLK_HW_INIT("ck_icn_p_wwdg2", "ck_icn_ls_mcu", &clk_stm32_gate_ops, 0),
> +};
> +
> +enum security_clk {
> + SECF_NONE,
What is the use of this single value enum?
> +};
> +
> +static const struct clock_config stm32mp25_clock_cfg[] = {
> + STM32_GATE_CFG(CK_BUS_ETH1, ck_icn_p_eth1, SECF_NONE),
> + STM32_GATE_CFG(CK_BUS_ETH2, ck_icn_p_eth2, SECF_NONE),
[....]
> +
> +static const struct of_device_id stm32mp25_match_data[] = {
> + {
> + .compatible = "st,stm32mp25-rcc",
> + .data = &stm32mp25_data,
> + },
One line please:
{ .compatible = "st,stm32mp25-rcc", .data = &stm32mp25_data, },
> + { }
> +};
> +MODULE_DEVICE_TABLE(of, stm32mp25_match_data);
> +
> +static int get_clock_deps(struct device *dev)
What is the explanation for this function?
> +{
> + static const char * const clock_deps_name[] = {
> + "hsi", "hse", "msi", "lsi", "lse",
> + };
> + int i;
> +
> + for (i = 0; i < ARRAY_SIZE(clock_deps_name); i++) {
> + struct clk *clk;
> +
> + clk = of_clk_get_by_name(dev_of_node(dev), clock_deps_name[i]);
> + if (IS_ERR(clk))
> + return PTR_ERR(clk);
> +
> + clk_put(clk);
> + }
> +
> + return 0;
> +}
> +
> +static int stm32mp25_rcc_clocks_probe(struct platform_device *pdev)
> +{
> + struct device *dev = &pdev->dev;
> + void __iomem *base;
> + int ret;
> +
> + ret = get_clock_deps(dev);
> + if (ret)
> + return ret;
> +
> + base = devm_of_iomap(dev, dev->of_node, 0, NULL);
Use platform device APIs.
> + if (WARN_ON(IS_ERR(base)))
> + return PTR_ERR(base);
> +
> + return stm32_rcc_init(dev, stm32mp25_match_data, base);
> +}
> +
> +static int stm32mp25_rcc_clocks_remove(struct platform_device *pdev)
> +{
> + struct device *dev = &pdev->dev;
> + struct device_node *child, *np = dev_of_node(dev);
> +
> + for_each_available_child_of_node(np, child)
> + of_clk_del_provider(child);
Add the providers with devm?
> +
> + return 0;
> +}
> +
> +static struct platform_driver stm32mp25_rcc_clocks_driver = {
> + .driver = {
> + .name = "stm32mp25_rcc",
> + .of_match_table = stm32mp25_match_data,
> + },
> + .probe = stm32mp25_rcc_clocks_probe,
> + .remove = stm32mp25_rcc_clocks_remove,
> +};
> +
> +static int __init stm32mp25_clocks_init(void)
> +{
> + return platform_driver_register(&stm32mp25_rcc_clocks_driver);
> +}
> +
> +core_initcall(stm32mp25_clocks_init);
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