lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <DM8PR11MB5751B02E235561D402D4C608B895A@DM8PR11MB5751.namprd11.prod.outlook.com>
Date: Thu, 21 Dec 2023 07:37:22 +0000
From: "Wang, Xiao W" <xiao.w.wang@...el.com>
To: Song Shuai <songshuaishuai@...ylab.org>, "paul.walmsley@...ive.com"
	<paul.walmsley@...ive.com>, "palmer@...belt.com" <palmer@...belt.com>,
	"aou@...s.berkeley.edu" <aou@...s.berkeley.edu>, "andy.chiu@...ive.com"
	<andy.chiu@...ive.com>, "greentime.hu@...ive.com" <greentime.hu@...ive.com>,
	"conor.dooley@...rochip.com" <conor.dooley@...rochip.com>,
	"guoren@...nel.org" <guoren@...nel.org>, "bjorn@...osinc.com"
	<bjorn@...osinc.com>, "heiko@...ech.de" <heiko@...ech.de>,
	"ruinland.tsai@...ive.com" <ruinland.tsai@...ive.com>
CC: "linux-riscv@...ts.infradead.org" <linux-riscv@...ts.infradead.org>,
	"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>
Subject: RE: [PATCH] riscv: vector: Check SR_SD before saving vstate



> -----Original Message-----
> From: Song Shuai <songshuaishuai@...ylab.org>
> Sent: Thursday, December 21, 2023 3:05 PM
> To: paul.walmsley@...ive.com; palmer@...belt.com;
> aou@...s.berkeley.edu; andy.chiu@...ive.com; greentime.hu@...ive.com;
> conor.dooley@...rochip.com; guoren@...nel.org;
> songshuaishuai@...ylab.org; bjorn@...osinc.com; Wang, Xiao W
> <xiao.w.wang@...el.com>; heiko@...ech.de; ruinland.tsai@...ive.com
> Cc: linux-riscv@...ts.infradead.org; linux-kernel@...r.kernel.org
> Subject: [PATCH] riscv: vector: Check SR_SD before saving vstate
> 
> The SD bit summarizes the dirty states of FS, VS, or XS fields,
> providing a "fast check" before saving fstate or vstate.
> 
> Let __switch_to_vector() check SD bit as __switch_to_fpu() does.

It looks a duplication of status check since the __switch_to_*() internally will check the ext specific status bit.
Can we just remove SR_SD check for the fpu() case?

BRs,
Xiao

> 
> Fixes: 3a2df6323def ("riscv: Add task switch support for vector")
> Signed-off-by: Song Shuai <songshuaishuai@...ylab.org>
> ---
>  arch/riscv/include/asm/vector.h | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
> 
> diff --git a/arch/riscv/include/asm/vector.h b/arch/riscv/include/asm/vector.h
> index 87aaef656257..d30fa56f67c6 100644
> --- a/arch/riscv/include/asm/vector.h
> +++ b/arch/riscv/include/asm/vector.h
> @@ -190,7 +190,8 @@ static inline void __switch_to_vector(struct
> task_struct *prev,
>  	struct pt_regs *regs;
> 
>  	regs = task_pt_regs(prev);
> -	riscv_v_vstate_save(prev, regs);
> +	if (unlikely(regs->status & SR_SD))
> +		riscv_v_vstate_save(prev, regs);
>  	riscv_v_vstate_restore(next, task_pt_regs(next));
>  }
> 
> --
> 2.20.1


Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ