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Message-ID: <20231221084358.3458713-3-jisheng.teoh@starfivetech.com>
Date: Thu, 21 Dec 2023 16:43:58 +0800
From: Ji Sheng Teoh <jisheng.teoh@...rfivetech.com>
To: Xingyu Wu <xingyu.wu@...rfivetech.com>, Samin Guo
<samin.guo@...rfivetech.com>, Wim Van Sebroeck <wim@...ux-watchdog.org>,
Guenter Roeck <linux@...ck-us.net>, Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>, Conor Dooley
<conor+dt@...nel.org>, Emil Renner Berthing <kernel@...il.dk>, Paul Walmsley
<paul.walmsley@...ive.com>, Palmer Dabbelt <palmer@...belt.com>, Albert Ou
<aou@...s.berkeley.edu>
CC: Ji Sheng Teoh <jisheng.teoh@...rfivetech.com>, Ley Foon Tan
<leyfoon.tan@...rfivetech.com>, <linux-watchdog@...r.kernel.org>,
<devicetree@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
<linux-riscv@...ts.infradead.org>
Subject: [PATCH v5 2/2] riscv: dts: starfive: jh8100: Add watchdog node
StarFive's JH8100 watchdog is based on JH7110, with JH8100 watchdog only
requiring one reset signal.
Signed-off-by: Ji Sheng Teoh <jisheng.teoh@...rfivetech.com>
---
arch/riscv/boot/dts/starfive/jh8100.dtsi | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/arch/riscv/boot/dts/starfive/jh8100.dtsi b/arch/riscv/boot/dts/starfive/jh8100.dtsi
index 9863c61324a0..657d8b79e708 100644
--- a/arch/riscv/boot/dts/starfive/jh8100.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh8100.dtsi
@@ -360,6 +360,15 @@ uart4: serial@...a0000 {
status = "disabled";
};
+ watchdog@...70000 {
+ compatible = "starfive,jh8100-wdt", "starfive,jh7110-wdt";
+ reg = <0x0 0x12270000 0x0 0x10000>;
+ clocks = <&syscrg_ne SYSCRG_NE_CLK_WDT_APB>,
+ <&syscrg_ne SYSCRG_NE_CLK_WDT>;
+ clock-names = "apb", "core";
+ resets = <&syscrg_ne SYSCRG_NE_RSTN_WDT0>;
+ };
+
syscrg_ne: syscrg_ne@...20000 {
compatible = "starfive,jh8100-syscrg-ne";
reg = <0x0 0x12320000 0x0 0x10000>;
--
2.25.1
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