linux-kernel - RE: [PATCH v1 06/16] clk: starfive: Add JH8100 System clock generator driver

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Message-ID: <442fd023a8bf43dfbb4991ac3eafbc05@EXMBX066.cuchost.com>
Date: Thu, 21 Dec 2023 00:45:40 +0000
From: JeeHeng Sia <jeeheng.sia@...rfivetech.com>
To: Emil Renner Berthing <emil.renner.berthing@...onical.com>,
	"kernel@...il.dk" <kernel@...il.dk>, "conor@...nel.org" <conor@...nel.org>,
	"robh+dt@...nel.org" <robh+dt@...nel.org>,
	"krzysztof.kozlowski+dt@...aro.org" <krzysztof.kozlowski+dt@...aro.org>,
	"paul.walmsley@...ive.com" <paul.walmsley@...ive.com>, "palmer@...belt.com"
	<palmer@...belt.com>, "aou@...s.berkeley.edu" <aou@...s.berkeley.edu>,
	"mturquette@...libre.com" <mturquette@...libre.com>, "sboyd@...nel.org"
	<sboyd@...nel.org>, "p.zabel@...gutronix.de" <p.zabel@...gutronix.de>, "Hal
 Feng" <hal.feng@...rfivetech.com>, Xingyu Wu <xingyu.wu@...rfivetech.com>
CC: "linux-riscv@...ts.infradead.org" <linux-riscv@...ts.infradead.org>,
	"devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
	"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
	"linux-clk@...r.kernel.org" <linux-clk@...r.kernel.org>, Leyfoon Tan
	<leyfoon.tan@...rfivetech.com>
Subject: RE: [PATCH v1 06/16] clk: starfive: Add JH8100 System clock generator
 driver



> -----Original Message-----
> From: Emil Renner Berthing <emil.renner.berthing@...onical.com>
> Sent: Wednesday, December 20, 2023 9:08 PM
> To: JeeHeng Sia <jeeheng.sia@...rfivetech.com>; Emil Renner Berthing <emil.renner.berthing@...onical.com>; kernel@...il.dk;
> conor@...nel.org; robh+dt@...nel.org; krzysztof.kozlowski+dt@...aro.org; paul.walmsley@...ive.com; palmer@...belt.com;
> aou@...s.berkeley.edu; mturquette@...libre.com; sboyd@...nel.org; p.zabel@...gutronix.de; Hal Feng
> <hal.feng@...rfivetech.com>; Xingyu Wu <xingyu.wu@...rfivetech.com>
> Cc: linux-riscv@...ts.infradead.org; devicetree@...r.kernel.org; linux-kernel@...r.kernel.org; linux-clk@...r.kernel.org; Leyfoon Tan
> <leyfoon.tan@...rfivetech.com>
> Subject: RE: [PATCH v1 06/16] clk: starfive: Add JH8100 System clock generator driver
> 
> JeeHeng Sia wrote:
[...]
> > >
> > > If you're just using this for testing on FPGAs you can create dummy fixed
> > > clocks in the device tree for the PLLs that this driver can consume.  Then
> > > later when you have a PLL driver you can replace those fixed clocks with the
> > > output of that driver.
> > The PLL fixed clocks were created in the C code. I interpret this message
> > as a suggestion to create a PLL fixed clock in the DT?
> 
> Yes, then you don't need to change the clock driver and its bindings but just
> need to update the clock references to the PLL driver once you have that.
Ok.
> 
> /Emil