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Message-ID: <20231221092824.1169453-1-chunyan.zhang@unisoc.com>
Date: Thu, 21 Dec 2023 17:28:22 +0800
From: Chunyan Zhang <chunyan.zhang@...soc.com>
To: Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski
<krzysztof.kozlowski+dt@...aro.org>,
Conor Dooley <conor+dt@...nel.org>
CC: <devicetree@...r.kernel.org>, Baolin Wang <baolin.wang@...ux.alibaba.com>,
Orson Zhai <orsonzhai@...il.com>,
Chunyan Zhang <chunyan.zhang@...soc.com>,
LKML <linux-kernel@...r.kernel.org>,
Chunyan Zhang <zhang.lyra@...il.com>
Subject: [PATCH 1/3] arm64: dts: sprd: Removed unused clock references from etm nodes
Remove these unused clock references to fix dtbs_check warnings:
etm@...40000: clocks: [[11], [35, 34], [36, 8]] is too long
etm@...40000: clock-names:1: 'atclk' was expected
etm@...40000: clock-names: ['apb_pclk', 'clk_cs', 'cs_src'] is too long
Signed-off-by: Chunyan Zhang <chunyan.zhang@...soc.com>
---
arch/arm64/boot/dts/sprd/ums512.dtsi | 32 ++++++++++++++--------------
1 file changed, 16 insertions(+), 16 deletions(-)
diff --git a/arch/arm64/boot/dts/sprd/ums512.dtsi b/arch/arm64/boot/dts/sprd/ums512.dtsi
index 024be594c47d..012b3a4bbe7c 100644
--- a/arch/arm64/boot/dts/sprd/ums512.dtsi
+++ b/arch/arm64/boot/dts/sprd/ums512.dtsi
@@ -682,8 +682,8 @@ etm0: etm@...40000 {
compatible = "arm,coresight-etm4x", "arm,primecell";
reg = <0 0x3f040000 0 0x1000>;
cpu = <&CPU0>;
- clocks = <&ext_26m>, <&aon_clk CLK_CSSYS>, <&pll2 CLK_TWPLL_512M>;
- clock-names = "apb_pclk", "clk_cs", "cs_src";
+ clocks = <&ext_26m>;
+ clock-names = "apb_pclk";
out-ports {
port {
@@ -699,8 +699,8 @@ etm1: etm@...40000 {
compatible = "arm,coresight-etm4x", "arm,primecell";
reg = <0 0x3f140000 0 0x1000>;
cpu = <&CPU1>;
- clocks = <&ext_26m>, <&aon_clk CLK_CSSYS>, <&pll2 CLK_TWPLL_512M>;
- clock-names = "apb_pclk", "clk_cs", "cs_src";
+ clocks = <&ext_26m>;
+ clock-names = "apb_pclk";
out-ports {
port {
@@ -716,8 +716,8 @@ etm2: etm@...40000 {
compatible = "arm,coresight-etm4x", "arm,primecell";
reg = <0 0x3f240000 0 0x1000>;
cpu = <&CPU2>;
- clocks = <&ext_26m>, <&aon_clk CLK_CSSYS>, <&pll2 CLK_TWPLL_512M>;
- clock-names = "apb_pclk", "clk_cs", "cs_src";
+ clocks = <&ext_26m>;
+ clock-names = "apb_pclk";
out-ports {
port {
@@ -733,8 +733,8 @@ etm3: etm@...40000 {
compatible = "arm,coresight-etm4x", "arm,primecell";
reg = <0 0x3f340000 0 0x1000>;
cpu = <&CPU3>;
- clocks = <&ext_26m>, <&aon_clk CLK_CSSYS>, <&pll2 CLK_TWPLL_512M>;
- clock-names = "apb_pclk", "clk_cs", "cs_src";
+ clocks = <&ext_26m>;
+ clock-names = "apb_pclk";
out-ports {
port {
@@ -750,8 +750,8 @@ etm4: etm@...40000 {
compatible = "arm,coresight-etm4x", "arm,primecell";
reg = <0 0x3f440000 0 0x1000>;
cpu = <&CPU4>;
- clocks = <&ext_26m>, <&aon_clk CLK_CSSYS>, <&pll2 CLK_TWPLL_512M>;
- clock-names = "apb_pclk", "clk_cs", "cs_src";
+ clocks = <&ext_26m>;
+ clock-names = "apb_pclk";
out-ports {
port {
@@ -767,8 +767,8 @@ etm5: etm@...40000 {
compatible = "arm,coresight-etm4x", "arm,primecell";
reg = <0 0x3f540000 0 0x1000>;
cpu = <&CPU5>;
- clocks = <&ext_26m>, <&aon_clk CLK_CSSYS>, <&pll2 CLK_TWPLL_512M>;
- clock-names = "apb_pclk", "clk_cs", "cs_src";
+ clocks = <&ext_26m>;
+ clock-names = "apb_pclk";
out-ports {
port {
@@ -784,8 +784,8 @@ etm6: etm@...40000 {
compatible = "arm,coresight-etm4x", "arm,primecell";
reg = <0 0x3f640000 0 0x1000>;
cpu = <&CPU6>;
- clocks = <&ext_26m>, <&aon_clk CLK_CSSYS>, <&pll2 CLK_TWPLL_512M>;
- clock-names = "apb_pclk", "clk_cs", "cs_src";
+ clocks = <&ext_26m>;
+ clock-names = "apb_pclk";
out-ports {
port {
@@ -801,8 +801,8 @@ etm7: etm@...40000 {
compatible = "arm,coresight-etm4x", "arm,primecell";
reg = <0 0x3f740000 0 0x1000>;
cpu = <&CPU7>;
- clocks = <&ext_26m>, <&aon_clk CLK_CSSYS>, <&pll2 CLK_TWPLL_512M>;
- clock-names = "apb_pclk", "clk_cs", "cs_src";
+ clocks = <&ext_26m>;
+ clock-names = "apb_pclk";
out-ports {
port {
--
2.41.0
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