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Message-ID: <13e0ce03-6de4-4f18-a290-f213f7490998@quicinc.com>
Date: Fri, 22 Dec 2023 16:25:52 +0800
From: Can Guo <quic_cang@...cinc.com>
To: Andrew Halaney <ahalaney@...hat.com>, Andy Gross <agross@...nel.org>,
Bjorn Andersson <andersson@...nel.org>,
Konrad Dybcio
<konrad.dybcio@...aro.org>,
Manivannan Sadhasivam <mani@...nel.org>,
"James
E.J. Bottomley" <jejb@...ux.ibm.com>,
"Martin K. Petersen"
<martin.petersen@...cle.com>,
Hannes Reinecke <hare@...e.de>, Janek Kotas
<jank@...ence.com>,
Alim Akhtar <alim.akhtar@...sung.com>,
Avri Altman
<avri.altman@....com>,
Bart Van Assche <bvanassche@....org>
CC: Will Deacon <will@...nel.org>, <linux-arm-msm@...r.kernel.org>,
<linux-scsi@...r.kernel.org>, <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH RFC v3 05/11] scsi: ufs: qcom: Perform read back after
writing CGC enable
On 12/22/2023 3:09 AM, Andrew Halaney wrote:
> Currently, the CGC enable bit is written and then an mb() is used to
> ensure that completes before continuing.
>
> mb() ensure that the write completes, but completion doesn't mean that
> it isn't stored in a buffer somewhere. The recommendation for
> ensuring this bit has taken effect on the device is to perform a read
> back to force it to make it all the way to the device. This is
> documented in device-io.rst and a talk by Will Deacon on this can
> be seen over here:
>
> https://youtu.be/i6DayghhA8Q?si=MiyxB5cKJXSaoc01&t=1678
>
> Let's do that to ensure the bit hits the device. Because the mb()'s
> purpose wasn't to add extra ordering (on top of the ordering guaranteed
> by writel()/readl()), it can safely be removed.
>
> Fixes: 81c0fc51b7a7 ("ufs-qcom: add support for Qualcomm Technologies Inc platforms")
> Signed-off-by: Andrew Halaney <ahalaney@...hat.com>
> ---
> drivers/ufs/host/ufs-qcom.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/ufs/host/ufs-qcom.c b/drivers/ufs/host/ufs-qcom.c
> index ab1ff7432d11..3db19591d008 100644
> --- a/drivers/ufs/host/ufs-qcom.c
> +++ b/drivers/ufs/host/ufs-qcom.c
> @@ -409,7 +409,7 @@ static void ufs_qcom_enable_hw_clk_gating(struct ufs_hba *hba)
> REG_UFS_CFG2);
>
> /* Ensure that HW clock gating is enabled before next operations */
> - mb();
> + ufshcd_readl(hba, REG_UFS_CFG2);
> }
>
> static int ufs_qcom_hce_enable_notify(struct ufs_hba *hba,
>
Reviewed-by: Can Guo <quic_cang@...cinc.com>
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