linux-kernel - [PATCH v10 1/4] dt-bindings: pwm: Add bindings for OpenCores PWM Controller

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Message-ID: <20231222094548.54103-2-william.qiu@starfivetech.com>
Date: Fri, 22 Dec 2023 17:45:45 +0800
From: William Qiu <william.qiu@...rfivetech.com>
To: <devicetree@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
	<linux-riscv@...ts.infradead.org>, <linux-pwm@...r.kernel.org>
CC: Emil Renner Berthing <kernel@...il.dk>, Rob Herring <robh+dt@...nel.org>,
	Thierry Reding <thierry.reding@...il.com>, Philipp Zabel
	<p.zabel@...gutronix.de>, Krzysztof Kozlowski
	<krzysztof.kozlowski+dt@...aro.org>, Conor Dooley <conor+dt@...nel.org>,
	Uwe Kleine-König <u.kleine-koenig@...gutronix.de>, "Hal
 Feng" <hal.feng@...rfivetech.com>, Paul Walmsley <paul.walmsley@...ive.com>,
	Palmer Dabbelt <palmer@...belt.com>, Albert Ou <aou@...s.berkeley.edu>,
	William Qiu <william.qiu@...rfivetech.com>
Subject: [PATCH v10 1/4] dt-bindings: pwm: Add bindings for OpenCores PWM Controller

Add bindings for OpenCores PWM Controller.

Signed-off-by: William Qiu <william.qiu@...rfivetech.com>
Reviewed-by: Hal Feng <hal.feng@...rfivetech.com>
Reviewed-by: Conor Dooley <conor.dooley@...rochip.com>
---
 .../bindings/pwm/opencores,pwm.yaml           | 55 +++++++++++++++++++
 1 file changed, 55 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/pwm/opencores,pwm.yaml

diff --git a/Documentation/devicetree/bindings/pwm/opencores,pwm.yaml b/Documentation/devicetree/bindings/pwm/opencores,pwm.yaml
new file mode 100644
index 000000000000..0b85dd861dfd
--- /dev/null
+++ b/Documentation/devicetree/bindings/pwm/opencores,pwm.yaml
@@ -0,0 +1,55 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pwm/opencores,pwm.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: OpenCores PWM controller
+
+maintainers:
+  - William Qiu <william.qiu@...rfivetech.com>
+
+description:
+  The OpenCores PTC ip core contains a PWM controller. When operating in PWM
+  mode, the PTC core generates binary signal with user-programmable low and
+  high periods. All PTC counters and registers are 32-bit.
+
+allOf:
+  - $ref: pwm.yaml#
+
+properties:
+  compatible:
+    items:
+      - enum:
+          - starfive,jh7100-pwm
+          - starfive,jh7110-pwm
+      - const: opencores,pwm-v1
+
+  reg:
+    maxItems: 1
+
+  clocks:
+    maxItems: 1
+
+  resets:
+    maxItems: 1
+
+  "#pwm-cells":
+    const: 3
+
+required:
+  - compatible
+  - reg
+  - clocks
+
+additionalProperties: false
+
+examples:
+  - |
+    pwm@...90000 {
+        compatible = "starfive,jh7110-pwm", "opencores,pwm-v1";
+        reg = <0x12490000 0x10000>;
+        clocks = <&clkgen 181>;
+        resets = <&rstgen 109>;
+        #pwm-cells = <3>;
+    };
-- 
2.34.1