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Message-ID: <ZYVo0X1q9w19qTwg@shikoro>
Date: Fri, 22 Dec 2023 11:45:37 +0100
From: Wolfram Sang <wsa@...nel.org>
To: Alain Volmat <alain.volmat@...s.st.com>
Cc: Andi Shyti <andi.shyti@...nel.org>, Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Conor Dooley <conor+dt@...nel.org>,
Maxime Coquelin <mcoquelin.stm32@...il.com>,
Alexandre Torgue <alexandre.torgue@...s.st.com>,
Pierre-Yves MORDRET <pierre-yves.mordret@...s.st.com>,
Conor Dooley <conor@...nel.org>,
Valentin Caron <valentin.caron@...s.st.com>,
linux-i2c@...r.kernel.org, devicetree@...r.kernel.org,
linux-stm32@...md-mailman.stormreply.com,
linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH v3 6/9] i2c: stm32f7: add support for stm32mp25 soc
On Fri, Dec 15, 2023 at 06:06:10PM +0100, Alain Volmat wrote:
> The stm32mp25 has only a single interrupt line used for both
> events and errors. In order to cope with that, reorganise the
> error handling code so that it can be called either from the
> common handler (used in case of SoC having only a single IT line)
> and the error handler for others.
> The CR1 register also embeds a new FMP bit, necessary when running
> at Fast Mode Plus frequency. This bit should be used instead of
> the SYSCFG bit used on other platforms.
> Add a new compatible to distinguish between the SoCs and two
> boolean within the setup structure in order to know if the
> platform has a single/multiple IT lines and if the FMP bit
> within CR1 is available or not.
>
> Signed-off-by: Valentin Caron <valentin.caron@...s.st.com>
> Signed-off-by: Alain Volmat <alain.volmat@...s.st.com>
Applied to for-next, thanks!
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