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Message-Id: <20231222111407.104270-4-fusibrandon13@gmail.com>
Date: Fri, 22 Dec 2023 12:14:07 +0100
From: Brandon Cheo Fusi <fusibrandon13@...il.com>
To: Andre Przywara <andre.przywara@....com>,
Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Conor Dooley <conor+dt@...nel.org>,
Paul Walmsley <paul.walmsley@...ive.com>,
Palmer Dabbelt <palmer@...belt.com>,
Albert Ou <aou@...s.berkeley.edu>,
Chen-Yu Tsai <wens@...e.org>,
Jernej Skrabec <jernej.skrabec@...il.com>,
Samuel Holland <samuel@...lland.org>,
Yangtao Li <tiny.windzz@...il.com>,
"Rafael J . Wysocki" <rafael@...nel.org>,
Viresh Kumar <viresh.kumar@...aro.org>,
Stephen Rothwell <sfr@...b.auug.org.au>
Cc: devicetree@...r.kernel.org,
linux-riscv@...ts.infradead.org,
linux-arm-kernel@...ts.infradead.org,
linux-sunxi@...ts.linux.dev,
linux-kernel@...r.kernel.org,
linux-pm@...r.kernel.org,
Brandon Cheo Fusi <fusibrandon13@...il.com>
Subject: [RFC PATCH v3 3/3] riscv: dts: allwinner: Fill in OPPs
Specify two voltage ranges, in order of increasing stability,
for each OPP.
Also define an nvmem cpu speed grade cell of length 2.
Link: https://github.com/Tina-Linux/linux-5.4/blob/master/arch/riscv/boot/dts/sunxi/sun20iw1p1.dtsi#L118-L133
Link: https://github.com/mangopi-sbc/tina-linux-5.4/blob/0d4903ebd9d2194ad914686d5b0fc1ddacf11a9d/arch/riscv/boot/dts/sunxi/sun20iw1p1.dtsi#L118-L182
Signed-off-by: Brandon Cheo Fusi <fusibrandon13@...il.com>
---
arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi | 19 ++++++++++++++++---
1 file changed, 16 insertions(+), 3 deletions(-)
diff --git a/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi b/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi
index 64c3c2e6c..7e2e015e0 100644
--- a/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi
+++ b/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi
@@ -39,16 +39,23 @@ cpu0_intc: interrupt-controller {
};
opp_table_cpu: opp-table-cpu {
- compatible = "operating-points-v2";
+ compatible = "allwinner,sun20i-d1-operating-points";
+ nvmem-cells = <&cpu_speed_grade>;
+ nvmem-cell-names = "speed";
+ opp-shared;
opp-408000000 {
opp-hz = /bits/ 64 <408000000>;
- opp-microvolt = <900000 900000 1100000>;
+
+ opp-microvolt-speed0 = <950000 950000 1100000>;
+ opp-microvolt-speed1 = <900000 900000 1100000>;
};
opp-1080000000 {
opp-hz = /bits/ 64 <1008000000>;
- opp-microvolt = <900000 900000 1100000>;
+
+ opp-microvolt-speed0 = <1100000>;
+ opp-microvolt-speed1 = <950000 950000 1100000>;
};
};
@@ -115,3 +122,9 @@ pmu {
<0x00000000 0x0000000f 0xffffffff 0xffffffff 0x00020000>;
};
};
+
+&sid {
+ cpu_speed_grade: cpu-speed-grade@0 {
+ reg = <0x00 0x2>;
+ };
+};
--
2.30.2
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