linux-kernel - Re: [PATCH 3/3] arm64: dts: exynos: gs101: define Multi Core Timer (MCT) node

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Date: Fri, 22 Dec 2023 10:59:37 -0600
From: Sam Protsenko <semen.protsenko@...aro.org>
To: Peter Griffin <peter.griffin@...aro.org>
Cc: robh+dt@...nel.org, krzysztof.kozlowski+dt@...aro.org, 
	daniel.lezcano@...aro.org, tglx@...utronix.de, conor+dt@...nel.org, 
	alim.akhtar@...sung.com, s.nawrocki@...sung.com, tomasz.figa@...il.com, 
	cw00.choi@...sung.com, mturquette@...libre.com, sboyd@...nel.org, 
	devicetree@...r.kernel.org, linux-arm-kernel@...ts.infradead.org, 
	linux-samsung-soc@...r.kernel.org, linux-clk@...r.kernel.org, 
	linux-kernel@...r.kernel.org, kernel-team@...roid.com, 
	tudor.ambarus@...aro.org, andre.draszik@...aro.org, saravanak@...gle.com, 
	willmcvicker@...gle.com
Subject: Re: [PATCH 3/3] arm64: dts: exynos: gs101: define Multi Core Timer
 (MCT) node

On Fri, Dec 22, 2023 at 10:54 AM Peter Griffin <peter.griffin@...aro.org> wrote:
>
> MCT has one global timer and 8 CPU local timers. The global timer
> can generate 4 interrupts, and each local timer can generate an
> interrupt making 12 interrupts in total.
>
> Signed-off-by: Peter Griffin <peter.griffin@...aro.org>
> ---

Reviewed-by: Sam Protsenko <semen.protsenko@...aro.org>

>  arch/arm64/boot/dts/exynos/google/gs101.dtsi | 20 ++++++++++++++++++++
>  1 file changed, 20 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/exynos/google/gs101.dtsi b/arch/arm64/boot/dts/exynos/google/gs101.dtsi
> index 9747cb3fa03a..4b09e740b58a 100644
> --- a/arch/arm64/boot/dts/exynos/google/gs101.dtsi
> +++ b/arch/arm64/boot/dts/exynos/google/gs101.dtsi
> @@ -292,6 +292,26 @@ cmu_misc: clock-controller@...10000 {
>                         clock-names = "dout_cmu_misc_bus", "dout_cmu_misc_sss";
>                 };
>
> +               timer@...50000 {
> +                       compatible = "google,gs101-mct",
> +                                    "samsung,exynos4210-mct";
> +                       reg = <0x10050000 0x800>;
> +                       interrupts = <GIC_SPI 753 IRQ_TYPE_LEVEL_HIGH 0>,
> +                                    <GIC_SPI 754 IRQ_TYPE_LEVEL_HIGH 0>,
> +                                    <GIC_SPI 755 IRQ_TYPE_LEVEL_HIGH 0>,
> +                                    <GIC_SPI 756 IRQ_TYPE_LEVEL_HIGH 0>,
> +                                    <GIC_SPI 757 IRQ_TYPE_LEVEL_HIGH 0>,
> +                                    <GIC_SPI 758 IRQ_TYPE_LEVEL_HIGH 0>,
> +                                    <GIC_SPI 759 IRQ_TYPE_LEVEL_HIGH 0>,
> +                                    <GIC_SPI 760 IRQ_TYPE_LEVEL_HIGH 0>,
> +                                    <GIC_SPI 761 IRQ_TYPE_LEVEL_HIGH 0>,
> +                                    <GIC_SPI 762 IRQ_TYPE_LEVEL_HIGH 0>,
> +                                    <GIC_SPI 763 IRQ_TYPE_LEVEL_HIGH 0>,
> +                                    <GIC_SPI 764 IRQ_TYPE_LEVEL_HIGH 0>;
> +                       clocks = <&ext_24_5m>, <&cmu_misc CLK_GOUT_MISC_MCT_PCLK>;
> +                       clock-names = "fin_pll", "mct";
> +               };
> +
>                 watchdog_cl0: watchdog@...60000 {
>                         compatible = "google,gs101-wdt";
>                         reg = <0x10060000 0x100>;
> --
> 2.43.0.472.g3155946c3a-goog
>