linux-kernel - [PATCH v2 0/3] phy: qcom: qmp-pcie: Add support for G3/G4 PCIe PHY for X1E80100

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Message-Id: <20231223-x1e80100-phy-pcie-v2-0-223c0556908a@linaro.org>
Date: Sat, 23 Dec 2023 13:55:20 +0200
From: Abel Vesa <abel.vesa@...aro.org>
To: Andy Gross <agross@...nel.org>, Bjorn Andersson <andersson@...nel.org>, 
 Konrad Dybcio <konrad.dybcio@...aro.org>, Vinod Koul <vkoul@...nel.org>, 
 Kishon Vijay Abraham I <kishon@...nel.org>, 
 Rob Herring <robh+dt@...nel.org>, 
 Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>, 
 Conor Dooley <conor+dt@...nel.org>, 
 Dmitry Baryshkov <dmitry.baryshkov@...aro.org>
Cc: linux-arm-msm@...r.kernel.org, linux-phy@...ts.infradead.org, 
 devicetree@...r.kernel.org, linux-kernel@...r.kernel.org, 
 Abel Vesa <abel.vesa@...aro.org>, 
 Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>
Subject: [PATCH v2 0/3] phy: qcom: qmp-pcie: Add support for G3/G4 PCIe PHY
 for X1E80100

This patchset adds the G4 tables and G4/G3 compatibles for X1E80100
platforms. Also adds the pciphy_v6_regs_layout to be used by the G4x2
phy and switches all the old QMP v6 PHYs to use the new regs layout.

Signed-off-by: Abel Vesa <abel.vesa@...aro.org>
---
Changes in v2:
- Added Krzysztof's R-b tag to first patch
- Added new patch which brings the pciephy_v6_regs_layout and made sure
  all older (existing) QMP v6 are using that.
- Switched the regs layout of the x1e80100 gen4x2 to the new
  pciephy_v6_regs_layout
- Link to v1: https://lore.kernel.org/r/20231222-x1e80100-phy-pcie-v1-0-b74ac13390bf@linaro.org

---
Abel Vesa (3):
      dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: Document the X1E80100 QMP PCIe PHYs
      phy: qcom: qmp-pcie: Add QMP v6 registers layout
      phy: qcom-qmp-pcie: Add support for X1E80100 g3x2 and g4x2 PCIE

 .../bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml   |   6 +
 drivers/phy/qualcomm/phy-qcom-qmp-pcie.c           | 186 ++++++++++++++++++++-
 2 files changed, 189 insertions(+), 3 deletions(-)
---
base-commit: 8a9be2a3cb673dba9d22311beb74be261f0b3f15
change-id: 20231201-x1e80100-phy-pcie-ef74adb9af30

Best regards,
-- 
Abel Vesa <abel.vesa@...aro.org>