linux-kernel - [PATCH v6 12/16] riscv: dts: sophgo: Add T-Head PMU extension for cv1800b

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Message-ID: <20231225103308.1557548-13-peterlin@andestech.com>
Date: Mon, 25 Dec 2023 18:33:04 +0800
From: Yu Chien Peter Lin <peterlin@...estech.com>
To: <acme@...nel.org>, <adrian.hunter@...el.com>, <ajones@...tanamicro.com>,
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Subject: [PATCH v6 12/16] riscv: dts: sophgo: Add T-Head PMU extension for cv1800b

xtheadpmu stands for T-Head Performance Monitor Unit extension.
Based on the added T-Head PMU ISA string, the SBI PMU driver
will make use of the non-standard irq source.

Signed-off-by: Yu Chien Peter Lin <peterlin@...estech.com>
Acked-by: Conor Dooley <conor.dooley@...rochip.com>
---
Changes v4 -> v5:
  - New patch
Changes v5 -> v6:
  - Include Conor's Acked-by
---
 arch/riscv/boot/dts/sophgo/cv1800b.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi b/arch/riscv/boot/dts/sophgo/cv1800b.dtsi
index aec6401a467b..8c0143f0a01b 100644
--- a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi
+++ b/arch/riscv/boot/dts/sophgo/cv1800b.dtsi
@@ -29,7 +29,7 @@ cpu0: cpu@0 {
 			riscv,isa = "rv64imafdc";
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
-					       "zifencei", "zihpm";
+					       "zifencei", "zihpm", "xtheadpmu";
 
 			cpu0_intc: interrupt-controller {
 				compatible = "riscv,cpu-intc";
-- 
2.34.1