linux-kernel - Re: [PATCH RFC v2 05/11] scsi: ufs: qcom: Perform read back after writing CGC enable'

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Message-ID: <20231227060448.GC2814@thinkpad>
Date: Wed, 27 Dec 2023 11:34:48 +0530
From: Manivannan Sadhasivam <mani@...nel.org>
To: Andrew Halaney <ahalaney@...hat.com>
Cc: Andy Gross <agross@...nel.org>, Bjorn Andersson <andersson@...nel.org>,
	Konrad Dybcio <konrad.dybcio@...aro.org>,
	"James E.J. Bottomley" <jejb@...ux.ibm.com>,
	"Martin K. Petersen" <martin.petersen@...cle.com>,
	Yaniv Gardi <ygardi@...eaurora.org>,
	Dov Levenglick <dovl@...eaurora.org>,
	Hannes Reinecke <hare@...e.de>,
	Subhash Jadavani <subhashj@...eaurora.org>,
	Gilad Broner <gbroner@...eaurora.org>,
	Venkat Gopalakrishnan <venkatg@...eaurora.org>,
	Janek Kotas <jank@...ence.com>,
	Alim Akhtar <alim.akhtar@...sung.com>,
	Avri Altman <avri.altman@....com>,
	Bart Van Assche <bvanassche@....org>,
	Anjana Hari <quic_ahari@...cinc.com>,
	Dolev Raviv <draviv@...eaurora.org>,
	Can Guo <quic_cang@...cinc.com>, Will Deacon <will@...nel.org>,
	linux-arm-msm@...r.kernel.org, linux-scsi@...r.kernel.org,
	linux-kernel@...r.kernel.org
Subject: Re: [PATCH RFC v2 05/11] scsi: ufs: qcom: Perform read back after
 writing CGC enable'

On Thu, Dec 21, 2023 at 12:25:22PM -0600, Andrew Halaney wrote:
> Currently, the CGC enable bit is written and then an mb() is used to
> ensure that completes before continuing.
> 
> mb() ensure that the write completes, but completion doesn't mean that
> it isn't stored in a buffer somewhere. The recommendation for
> ensuring this bit has taken effect on the device is to perform a read
> back to force it to make it all the way to the device. This is
> documented in device-io.rst and a talk by Will Deacon on this can
> be seen over here:
> 
>     https://youtu.be/i6DayghhA8Q?si=MiyxB5cKJXSaoc01&t=1678
> 
> Let's do that to ensure the bit hits the device. Because the mb()'s
> purpose wasn't to add extra ordering (on top of the ordering guaranteed
> by writel()/readl()), it can safely be removed.
> 
> Fixes: 81c0fc51b7a7 ("ufs-qcom: add support for Qualcomm Technologies Inc platforms")
> Signed-off-by: Andrew Halaney <ahalaney@...hat.com>

For this patch, a read back would make sense since I'm not sure if the ICE block
getting enabled afterwards is in the same domain or not.

Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@...aro.org>

- Mani

> ---
>  drivers/ufs/host/ufs-qcom.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/ufs/host/ufs-qcom.c b/drivers/ufs/host/ufs-qcom.c
> index ab1ff7432d11..3db19591d008 100644
> --- a/drivers/ufs/host/ufs-qcom.c
> +++ b/drivers/ufs/host/ufs-qcom.c
> @@ -409,7 +409,7 @@ static void ufs_qcom_enable_hw_clk_gating(struct ufs_hba *hba)
>  		    REG_UFS_CFG2);
>  
>  	/* Ensure that HW clock gating is enabled before next operations */
> -	mb();
> +	ufshcd_readl(hba, REG_UFS_CFG2);
>  }
>  
>  static int ufs_qcom_hce_enable_notify(struct ufs_hba *hba,
> 
> -- 
> 2.43.0
> 

-- 
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