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Message-Id: <20231228084642.1765-3-jszhang@kernel.org>
Date: Thu, 28 Dec 2023 16:46:42 +0800
From: Jisheng Zhang <jszhang@...nel.org>
To: Will Deacon <will@...nel.org>,
"Aneesh Kumar K . V" <aneesh.kumar@...ux.ibm.com>,
Andrew Morton <akpm@...ux-foundation.org>,
Nick Piggin <npiggin@...il.com>,
Peter Zijlstra <peterz@...radead.org>,
Catalin Marinas <catalin.marinas@....com>,
Paul Walmsley <paul.walmsley@...ive.com>,
Palmer Dabbelt <palmer@...belt.com>,
Albert Ou <aou@...s.berkeley.edu>,
Arnd Bergmann <arnd@...db.de>
Cc: linux-arch@...r.kernel.org,
linux-mm@...ck.org,
linux-arm-kernel@...ts.infradead.org,
linux-kernel@...r.kernel.org,
linux-riscv@...ts.infradead.org
Subject: [PATCH 2/2] riscv: tlb: avoid tlb flushing if fullmm == 1
The mmu_gather code sets fullmm=1 when tearing down the entire address
space for an mm_struct on exit or execve. So if the underlying platform
supports ASID, the tlb flushing can be avoided because the ASID
allocator will never re-allocate a dirty ASID.
Use the performance of Process creation in unixbench on T-HEAD TH1520
platform is improved by about 4%.
Signed-off-by: Jisheng Zhang <jszhang@...nel.org>
---
arch/riscv/include/asm/tlb.h | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/arch/riscv/include/asm/tlb.h b/arch/riscv/include/asm/tlb.h
index 1eb5682b2af6..35f3c214332e 100644
--- a/arch/riscv/include/asm/tlb.h
+++ b/arch/riscv/include/asm/tlb.h
@@ -12,10 +12,19 @@ static void tlb_flush(struct mmu_gather *tlb);
#define tlb_flush tlb_flush
#include <asm-generic/tlb.h>
+#include <asm/mmu_context.h>
static inline void tlb_flush(struct mmu_gather *tlb)
{
#ifdef CONFIG_MMU
+ /*
+ * If ASID is supported, the ASID allocator will either invalidate the
+ * ASID or mark it as used. So we can avoid TLB invalidation when
+ * pulling down a full mm.
+ */
+ if (static_branch_likely(&use_asid_allocator) && tlb->fullmm)
+ return;
+
if (tlb->fullmm || tlb->need_flush_all)
flush_tlb_mm(tlb->mm);
else
--
2.40.0
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