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Message-ID: <20231228125805.661725-9-tudor.ambarus@linaro.org>
Date: Thu, 28 Dec 2023 12:58:01 +0000
From: Tudor Ambarus <tudor.ambarus@...aro.org>
To: peter.griffin@...aro.org,
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Tudor Ambarus <tudor.ambarus@...aro.org>
Subject: [PATCH v2 08/12] arm64: dts: exynos: gs101: remove reg-io-width from serial
Remove the reg-io-width property in order to comply with the bindings.
The entire bus (PERIC) on which the GS101 serial resides only allows
32-bit register accesses. The reg-io-width dt property is disallowed
for the "google,gs101-uart" compatible and instead the iotype is
inferred from the compatible.
Signed-off-by: Tudor Ambarus <tudor.ambarus@...aro.org>
---
v2: new patch
arch/arm64/boot/dts/exynos/google/gs101.dtsi | 1 -
1 file changed, 1 deletion(-)
diff --git a/arch/arm64/boot/dts/exynos/google/gs101.dtsi b/arch/arm64/boot/dts/exynos/google/gs101.dtsi
index 9747cb3fa03a..2c27c3cb9237 100644
--- a/arch/arm64/boot/dts/exynos/google/gs101.dtsi
+++ b/arch/arm64/boot/dts/exynos/google/gs101.dtsi
@@ -366,7 +366,6 @@ usi_uart: usi@...000c0 {
serial_0: serial@...00000 {
compatible = "google,gs101-uart";
reg = <0x10a00000 0xc0>;
- reg-io-width = <4>;
interrupts = <GIC_SPI 634
IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&dummy_clk 0>, <&dummy_clk 0>;
--
2.43.0.472.g3155946c3a-goog
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