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Message-ID: <202312300330.yMjWp5Pr-lkp@intel.com>
Date: Sat, 30 Dec 2023 04:02:04 +0800
From: kernel test robot <lkp@...el.com>
To: Chunyan Zhang <chunyan.zhang@...soc.com>,
Stephen Boyd <sboyd@...nel.org>, Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzk@...nel.org>,
Conor Dooley <conor+dt@...nel.org>
Cc: oe-kbuild-all@...ts.linux.dev, linux-clk@...r.kernel.org,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
Orson Zhai <orsonzhai@...il.com>,
Baolin Wang <baolin.wang@...ux.alibaba.com>,
Chunyan Zhang <chunyan.zhang@...soc.com>
Subject: Re: [PATCH 3/3] clk: sprd: add support for UMS9620
Hi Chunyan,
kernel test robot noticed the following build warnings:
[auto build test WARNING on clk/clk-next]
[also build test WARNING on robh/for-next krzk-dt/for-next linus/master v6.7-rc7 next-20231222]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url: https://github.com/intel-lab-lkp/linux/commits/Chunyan-Zhang/dt-bindings-clk-sprd-Add-UMS9620-support/20231229-165718
base: https://git.kernel.org/pub/scm/linux/kernel/git/clk/linux.git clk-next
patch link: https://lore.kernel.org/r/20231229085156.1490233-4-chunyan.zhang%40unisoc.com
patch subject: [PATCH 3/3] clk: sprd: add support for UMS9620
config: arm64-defconfig (https://download.01.org/0day-ci/archive/20231230/202312300330.yMjWp5Pr-lkp@intel.com/config)
compiler: aarch64-linux-gcc (GCC) 13.2.0
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20231230/202312300330.yMjWp5Pr-lkp@intel.com/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@...el.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202312300330.yMjWp5Pr-lkp@intel.com/
All warnings (new ones prefixed by >>):
>> drivers/clk/sprd/ums9620-clk.c:2642:37: warning: 'depth_parents' defined but not used [-Wunused-const-variable=]
2642 | static const struct clk_parent_data depth_parents[] = {
| ^~~~~~~~~~~~~
>> drivers/clk/sprd/ums9620-clk.c:1671:37: warning: 'pmu_26m_parents' defined but not used [-Wunused-const-variable=]
1671 | static const struct clk_parent_data pmu_26m_parents[] = {
| ^~~~~~~~~~~~~~~
vim +/depth_parents +2642 drivers/clk/sprd/ums9620-clk.c
2568
2569 /* mm clocks */
2570 static const struct clk_parent_data vdsp_parents[] = {
2571 { .fw_name = "ext-26m" },
2572 { .hw = &tgpll_307m2.hw },
2573 { .hw = &tgpll_512m.hw },
2574 { .hw = &tgpll_614m4.hw },
2575 { .hw = &v4nrpll_819m2.hw },
2576 { .hw = &vdsppll.common.hw }
2577 };
2578 static SPRD_MUX_CLK_DATA(vdsp, "vdsp", vdsp_parents, 0x28,
2579 0, 2, CLK_SET_RATE_NO_REPARENT);
2580 static SPRD_DIV_CLK_HW(vdsp_m, "vdsp-m", &vdsp.common.hw, 0x30,
2581 0, 2, 0);
2582
2583 static const struct clk_parent_data vdma_parents[] = {
2584 { .fw_name = "ext-26m" },
2585 { .hw = &tgpll_153m6.hw },
2586 { .hw = &tgpll_256m.hw },
2587 { .hw = &tgpll_307m2.hw },
2588 { .hw = &v4nrpll_409m6.hw },
2589 { .hw = &tgpll_512m.hw },
2590 };
2591 static SPRD_MUX_CLK_DATA(vdma, "vdma", vdma_parents, 0x40,
2592 0, 3, UMS9620_MUX_FLAG);
2593
2594 static const struct clk_parent_data vdsp_mtx_data_parents[] = {
2595 { .hw = &tgpll_153m6.hw },
2596 { .hw = &tgpll_307m2.hw },
2597 { .hw = &v4nrpll_409m6.hw },
2598 { .hw = &tgpll_512m.hw },
2599 };
2600 static SPRD_MUX_CLK_DATA(vdsp_mtx_data, "vdsp-mtx-data", vdsp_mtx_data_parents,
2601 0x58, 0, 2, UMS9620_MUX_FLAG);
2602
2603 static const struct clk_parent_data vdsp_blk_cfg_parents[] = {
2604 { .fw_name = "ext-26m" },
2605 { .hw = &tgpll_48m.hw },
2606 { .hw = &tgpll_64m.hw },
2607 { .hw = &tgpll_96m.hw },
2608 { .hw = &tgpll_128m.hw },
2609 };
2610 static SPRD_MUX_CLK_DATA(vdsp_blk_cfg, "vdsp-blk-cfg", vdsp_blk_cfg_parents,
2611 0x64, 0, 3, UMS9620_MUX_FLAG);
2612
2613 static const struct clk_parent_data mm_uart_parents[] = {
2614 { .fw_name = "ext-26m" },
2615 { .hw = &tgpll_48m.hw },
2616 { .hw = &tgpll_51m2.hw },
2617 { .hw = &tgpll_96m.hw },
2618 };
2619 static SPRD_MUX_CLK_DATA(mm_uart, "mm-uart", mm_uart_parents, 0x70,
2620 0, 2, UMS9620_MUX_FLAG);
2621
2622 static const struct clk_parent_data isp_parents[] = {
2623 { .hw = &tgpll_153m6.hw },
2624 { .hw = &tgpll_256m.hw },
2625 { .hw = &tgpll_307m2.hw },
2626 { .hw = &v4nrpll_409m6.hw },
2627 { .hw = &tgpll_512m.hw },
2628 };
2629 static SPRD_MUX_CLK_DATA(isp, "isp", isp_parents, 0x7c,
2630 0, 3, UMS9620_MUX_FLAG);
2631
2632 static const struct clk_parent_data cpp_parents[] = {
2633 { .hw = &tgpll_128m.hw },
2634 { .hw = &tgpll_192m.hw },
2635 { .hw = &tgpll_256m.hw },
2636 { .hw = &tgpll_307m2.hw },
2637 { .hw = &tgpll_384m.hw },
2638 };
2639 static SPRD_MUX_CLK_DATA(cpp, "cpp", cpp_parents, 0x88,
2640 0, 3, UMS9620_MUX_FLAG);
2641
> 2642 static const struct clk_parent_data depth_parents[] = {
2643 { .hw = &tgpll_128m.hw },
2644 { .hw = &tgpll_192m.hw },
2645 { .hw = &tgpll_256m.hw },
2646 { .hw = &tgpll_307m2.hw },
2647 { .hw = &tgpll_384m.hw },
2648 };
2649 static SPRD_MUX_CLK_DATA(depth, "depth", cpp_parents, 0xa0,
2650 0, 3, UMS9620_MUX_FLAG);
2651
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