linux-kernel - [v2 02/10] RISC-V: Add FIRMWARE_READ

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Message-Id: <20231229214950.4061381-3-atishp@rivosinc.com>
Date: Fri, 29 Dec 2023 13:49:42 -0800
From: Atish Patra <atishp@...osinc.com>
To: linux-kernel@...r.kernel.org
Cc: Atish Patra <atishp@...osinc.com>,
	Conor Dooley <conor.dooley@...rochip.com>,
	Anup Patel <anup@...infault.org>,
	Albert Ou <aou@...s.berkeley.edu>,
	Alexandre Ghiti <alexghiti@...osinc.com>,
	Andrew Jones <ajones@...tanamicro.com>,
	Atish Patra <atishp@...shpatra.org>,
	Guo Ren <guoren@...nel.org>,
	Heiko Stuebner <heiko@...ech.de>,
	kvm-riscv@...ts.infradead.org,
	kvm@...r.kernel.org,
	linux-riscv@...ts.infradead.org,
	Mark Rutland <mark.rutland@....com>,
	Palmer Dabbelt <palmer@...belt.com>,
	Paul Walmsley <paul.walmsley@...ive.com>,
	Will Deacon <will@...nel.org>
Subject: [v2 02/10] RISC-V: Add FIRMWARE_READ_HI definition

SBI v2.0 added another function to SBI PMU extension to read
the upper bits of a counter with width larger than XLEN.

Add the definition for that function.

Acked-by: Conor Dooley <conor.dooley@...rochip.com>
Reviewed-by: Anup Patel <anup@...infault.org>
Signed-off-by: Atish Patra <atishp@...osinc.com>
---
 arch/riscv/include/asm/sbi.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h
index b6f898c56940..914eacc6ba2e 100644
--- a/arch/riscv/include/asm/sbi.h
+++ b/arch/riscv/include/asm/sbi.h
@@ -122,6 +122,7 @@ enum sbi_ext_pmu_fid {
 	SBI_EXT_PMU_COUNTER_START,
 	SBI_EXT_PMU_COUNTER_STOP,
 	SBI_EXT_PMU_COUNTER_FW_READ,
+	SBI_EXT_PMU_COUNTER_FW_READ_HI,
 };
 
 union sbi_pmu_ctr_info {
-- 
2.34.1