Message-ID: <2e937686-d579-4553-ada8-17a1cb1237cf@linaro.org>
Date: Sat, 30 Dec 2023 13:28:25 +0100
From: Konrad Dybcio <konrad.dybcio@...aro.org>
To: Manivannan Sadhasivam <manivannan.sadhasivam@...aro.org>,
 Johan Hovold <johan@...nel.org>
Cc: Bjorn Andersson <andersson@...nel.org>, Rob Herring <robh+dt@...nel.org>,
 Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
 Conor Dooley <conor+dt@...nel.org>, Johan Hovold <johan+linaro@...nel.org>,
 Marijn Suijten <marijn.suijten@...ainline.org>,
 linux-arm-msm@...r.kernel.org, devicetree@...r.kernel.org,
 linux-kernel@...r.kernel.org,
 Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>,
 Konrad Dybcio <konrad.dybcio@...ainline.org>
Subject: Re: [PATCH 1/3] arm64: dts: qcom: sc8280xp: Fix PCIe PHY
 power-domains

On 29.12.2023 18:03, Manivannan Sadhasivam wrote:
> On Fri, Dec 29, 2023 at 12:24:55PM +0100, Johan Hovold wrote:
>> On Wed, Dec 27, 2023 at 11:28:26PM +0100, Konrad Dybcio wrote:
>>> The PCIe GDSCs are only related to the RCs. The PCIe PHYs on the other
>>> hand, are powered by VDD_MX and their specific VDDA_PHY/PLL regulators.
>>
>> No, that does not seem to be entirely correct. I added the power-domains
>> here precisely because they were needed to enable the PHYs.
>>
>> This is something I stumbled over when trying to figure out how to
>> add support for the second lane pair (i.e. four-lane mode), and I just
>> went back and confirmed that this is still the case.
>>
>> If you try to enable one of these PHYs without the corresponding GDSC
>> being enabled, you end up with:
>>
>> [   37.709324] ------------[ cut here ]------------
>> [   37.718196] gcc_pcie_3b_aux_clk status stuck at 'off'
>> [   37.718205] WARNING: CPU: 4 PID: 482 at drivers/clk/qcom/clk-branch.c:86 clk_branch_wait+0x144/0x15c
>> 	
> 
> Technically this patch is correct. PHYs are backed by MX domain only and not
> GDSCs. Only the controllers (PCIe, UFS, USB) are backed by GDSCs. The fact that
> you are seeing issue with PCIe Aux clock suggests me that this clock may not be
> applicable to the PHY but it needs to be enabled for working of the PHY somehow.
> I'll try to find the details on how exactly it is needed.
> 
> But if I get the answer like, "This clock is also sourced to PHY directly", then
> we may need to add dual power domain for PHY (both GDSC and MX).
> 
>> Now, you may or may not want to describe the above in the devicetree,
>> but this makes it sound like you're trying to work around an issue with
>> the current Linux implementation.

I did a bit of experimentation, and.. I think that the PHY itself doesn't
need the GDSC to be enabled.

However.

The AUX clock requires the GDSC to be enabled and the PHY will fail to
power on if this clock is disabled.

That makes me wonder if representing the PCIe PHY as a wholly separate
device (instead of e.g. it being a subdev of PCIe RC) is even correct..

>>
> 
> Adding MX domain to PHY in devicetree is definitely not a workaround. It is the
> actual hardware representation. MX is the always on domain, and when CX collapse
> happens during suspend state, it will ensure that all the analog components
> (like PHY) are kept powered on. Otherwise, we will see link down issues.
> 
> But, I heard from Qcom that _only_ on this platform, MX is not backing the PCIe
> PHY. I can correlate that with my encounter with PCIe issues after forcing CX
> power collapse.
I've heard otherwise, the PHY itself is powered by MX, but CX needs
to be (should be?) enabled for communication with the RC (which itself
needs CX to be up to function).

Konrad

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